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![]() Date: 2013-07-27 22:48:57Instruction set architectures Itanium Branch predication Reduced instruction set computing Very long instruction word Intel 64-bit Compiler Microprocessor Computer architecture Computing Computer hardware | Add to Reading List |
![]() | Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications William Kreahling Western Carolina UniversityDocID: 1graT - View Document |
![]() | Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FLDocID: 1fQcm - View Document |
![]() | Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052DocID: 18TIq - View Document |
![]() | Parallel Architectures and Compilation Techniques PACT 2001DocID: 17IW6 - View Document |
![]() | Microsoft Word - IHD_OS_Vol 4_Part 2_July_28_10.docDocID: 15Evy - View Document |