<--- Back to Details
First PageDocument Content
Instruction set architectures / Itanium / Branch predication / Reduced instruction set computing / Very long instruction word / Intel / 64-bit / Compiler / Microprocessor / Computer architecture / Computing / Computer hardware
Date: 2013-07-27 22:48:57
Instruction set architectures
Itanium
Branch predication
Reduced instruction set computing
Very long instruction word
Intel
64-bit
Compiler
Microprocessor
Computer architecture
Computing
Computer hardware

Hot Chips IA64 Tutorial, part 1

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 301,17 KB

Share Document on Facebook

Similar Documents

Branch predictor / Branch misprediction / Assembly languages / Instruction set / Branch predication / Compiler optimization / ARM architecture / Processor register / Classic RISC pipeline / Computer architecture / Central processing unit / Instruction set architectures

Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications William Kreahling Western Carolina University

DocID: 1graT - View Document

Compiler optimizations / Assembly languages / Instruction scheduling / Reduced instruction set computing / Instruction set / Branch predication / Register renaming / Very long instruction word / Addressing mode / Computer architecture / Computing / Computer engineering

Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL

DocID: 1fQcm - View Document

Computer hardware / Computer memory / Software pipelining / AMD 10h / Loop unwinding / CPU cache / Branch predication / Explicitly parallel instruction computing / Compiler optimizations / Computing / Computer architecture

Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052

DocID: 18TIq - View Document

Central processing unit / Parallel computing / Branch predication / Instruction set / Branch misprediction / Superscalar / Computer architecture / Computing / Computer engineering

Parallel Architectures and Compilation Techniques PACT 2001

DocID: 17IW6 - View Document

Central processing unit / Addressing mode / Machine code / Instruction set / Branch predication / Computer architecture / Instruction set architectures / Assembly languages

Microsoft Word - IHD_OS_Vol 4_Part 2_July_28_10.doc

DocID: 15Evy - View Document