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OpenRISC
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#	Item
1	OpTiMSoC User Guide June 7, 2016 Document Changes Add to Reading List Source URL: www.optimsoc.org Language: English - Date: 2016-06-07 08:44:38 Software Embedded microprocessors OpenRISC SystemC Package manager Field-programmable gate array Verilator Git Linux distribution Nullsoft Scriptable Install System Installation
2	PDF Document Add to Reading List Source URL: openrisc.io Language: English - Date: 2016-08-09 21:38:18
3	PDF Document Add to Reading List Source URL: openrisc.io Language: English - Date: 2015-11-29 11:42:36
4	FEATURE OPENCORES: DIY CPUS Designing and implementing your own CPU or System-on-Chip brings benefits to thousands of researchers and forward-looking businesses, and is being adopted by a growing number of hobbyists. Ri Add to Reading List Source URL: www.linuxvoice.com Language: English - Date: 2015-02-09 09:27:26 Electronic design Embedded microprocessors OpenRISC Microprocessors Logic design OpenCores LEON Field-programmable gate array OpenSPARC Electronic engineering Computer hardware Electronics
5	Softcores for FPGA: The Free and Open Source Alternatives Jeremy Bennett and Simon Cook, Embecosm Abstract Open source soft cores have reached a degree of maturity. You can find them in products as diverse as a Samsung s Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-11-20 07:44:14 Embedded microprocessors GNU Project OpenRISC Computer law LEON Copyleft OpenCores OpenSPARC Verilator Electronic engineering Computer hardware Electronics
6	Who Ate My Battery? Why software engineers are the key to low power system design Jeremy Bennett, Embecosm Abstract Despite a decade of innovative development, and despite improvements in battery technology, a modern sma Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-01-16 23:54:46 Integrated circuits IEEE standards Electronics manufacturing Joint Test Action Group Debuggers PSoC Field-programmable gate array Programmer OpenRISC Electronic engineering Electronics Embedded systems
7	Building a Loosely Timed SoC Model with OSCI TLM 2.0 A Case Study Using an Open Source ISS and Linux 2.6 Kernel Jeremy Bennett Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-01-16 23:54:44 Transaction-level modeling Embedded microprocessors Joint Test Action Group OpenRISC Universal asynchronous receiver/transmitter Embedded system Coupling System on a chip Catapult C Electronic engineering Electronics SystemC
8	Integrating the GNU Debugger with Cycle Accurate Models A Case Study using a Verilator SystemC Model of the OpenRISCJeremy Bennett Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-01-16 23:54:44 Debuggers IEEE standards SystemC OpenRISC Verilator GNU Debugger Joint Test Action Group OpenCores Gdbserver Electronic engineering Electronics Computing
9	Open Source Software Meets Open Source Hardware: The OpenRISC 1000 Jeremy Bennett, Embecosm Abstract This paper presents the OpenRISC 1200, an open source implementation of the OpenRISC 1000 architecture, verified using Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-01-16 23:54:46 Hardware description languages Embedded microprocessors Hardware verification languages OpenRISC Debuggers Verilator Logic design OpenCores SystemC Electronic engineering Electronics Software
10	High Performance SoC Modeling with Verilator A Tutorial for Cycle Accurate SystemC Model Creation and Optimization Jeremy Bennett Add to Reading List Source URL: www.embecosm.com Language: English - Date: 2013-01-16 23:54:44 Verilator OpenRISC OpenCores Verilog GTKWave Field-programmable gate array VHDL Catapult C OVPsim Electronic engineering Hardware description languages SystemC

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