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Multiprocessor
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#	Item
91	Using the duplicaticity of a taskgraph to select a suitable multiprocessor scheduling strategy Frode Eika Sandnes Dept. Computer Science, Faculty of Engineering Oslo University College, Cort Adelers gate 30 N-0254 Oslo, Add to Reading List Source URL: www.nik.no Language: English - Date: 2002-10-07 01:29:27 Mathematical optimization Theoretical computer science Mathematics Directed acyclic graph Multiprocessor scheduling Job shop scheduling Distributed computing Topology Graph coloring Graph theory Operations research Scheduling
92	The NUMAchine Multiprocessor: Design and Analysis Robin Grindley A thesis submitted in conformity with the requirements Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-11-29 17:16:53 Central processing unit Parallel computing Computer memory Concurrent computing CPU cache Scalable Coherent Interface Non-Uniform Memory Access Cache coherence Microarchitecture Computing Computer hardware Computer architecture
93	Design and Implementation of the NUMAchine Multiprocessor A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian , S. Srbljic , M. Stumm, Z. Vranesic and Z. Zilic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:54 Parallel computing Cache coherency Computer buses CPU cache Central processing unit Non-Uniform Memory Access Cache coherence Cache Conventional PCI Computing Computer hardware Computer memory
94	The NUMAchine Multiprocessor R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vra Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 2000-09-02 04:07:38 CPU cache Non-Uniform Memory Access Cache coherence Speedup Cache-only memory architecture SMP - Symmetric Multiprocessor System Cache Memory hierarchy Scalable Coherent Interface Computing Parallel computing Computer memory
95	Helping in a multiprocessor environment Michael Hohmuth Michael Peter Dresden University of Technology Add to Reading List Source URL: os.inf.tu-dresden.de Language: English - Date: 2001-09-19 11:02:15 Spinlock Thread Scheduling Lock Load Critical section Context switch Test-and-set Non-blocking algorithm Computing Concurrency control Concurrent computing
96	Hardware Performance Monitoring in Memory of NUMAchine Multiprocessor by Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:35 Computer memory Computer architecture CPU cache Cache Parallel computing Hardware performance counter Computing Central processing unit Computer hardware
97	MULTIPROCESSOR IMPLEMENTATION OF A TEXTURE SEGMENTATION SCHEME FOR SATELLITE RADAR IMAGES R D Paget (+) I D Longstaff (+) B C Lovell (+) (+) Department of Electrical and Computer Engineering, University of Queensland, Add to Reading List Source URL: www.texturesynthesis.com Language: English - Date: 2009-01-20 17:53:54 Cluster analysis Mean-shift Hierarchical clustering Quadtree K-means clustering Consensus clustering Statistics Image processing Segmentation
98	Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System ∗ Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-05-31 00:24:02 System software Central processing unit Application programming interfaces Thread Ring Kernel Interrupt handler System call Mach Computing Computer architecture Concurrent computing
99	Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies∗ Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:45:45 CPU cache Dynamic random-access memory Memory refresh EDRAM Cache MESI protocol Random-access memory Memory hierarchy Computer data storage Computer memory Computer hardware Computing
100	Theme Feature . A Single-Chip Multiprocessor Add to Reading List Source URL: www-hydra.stanford.edu Language: English - Date: 1998-03-07 07:33:31 Parallel computing Central processing unit Microprocessors Threads Simultaneous multithreading Superscalar Multithreading Microarchitecture Multi-core processor Computing Computer architecture Computer hardware

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