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Microarchitecture
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#	Item
61	EN164: Design of Computing Systems Lecture 12: Processor / Single-Cycle Design 1 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:52 Computer engineering Datapath Microarchitecture MIPS architecture Register file Instruction set Classic RISC pipeline Computer architecture Central processing unit Computer hardware
62	Modeling and Characterizing Power Variability in Multicore Architectures Ke Meng Frank Huebbers Russ Joseph Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2008-12-17 09:58:48 Microprocessors Central processing unit Computer architecture Integrated circuits Multi-core processor CPU cache Microarchitecture AMD 10h CPU design Electronic engineering Electronics Computer hardware
63	Exploiting Locality to Improve Circuit-level Timing Speculation Jing Xin, Northwestern University and Russ Joseph, Northwestern University Abstract—Circuit-level timing speculation has been proposed as a technique to r Add to Reading List Source URL: users.eecs.northwestern.edu Language: English - Date: 2010-04-13 16:41:18 Central processing unit Computer memory Instruction set architectures CPU cache Cache Microarchitecture Intel Core DEC Alpha Computer architecture Computer hardware Computer engineering
64	RE SE A RCH F E AT U RE Concurrent Average Memory Access Time Xian-He Sun and Dawei Wang, Add to Reading List Source URL: www.cs.iit.edu Language: English - Date: 2014-05-30 12:12:22 Computer architecture Computer memory Microprocessors Threads CPU cache Cache Memory hierarchy Microarchitecture Parallel computing Computer hardware Computing Central processing unit
65	D Intel® XScale™ Microarchitecture Technical Summary Product Features Add to Reading List Source URL: www.a4com.de Language: English - Date: 2006-12-21 09:47:13 Computing ARM architecture XScale Control register CPU cache Microarchitecture Instruction set Processor register Comparison of CPU architectures Computer architecture Computer hardware Central processing unit
66	Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications Timothy Sherwood Erez Perelman Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:48 Central processing unit Compiler construction Computer memory Software optimization CPU cache Profiling Microarchitecture Compiler optimization Branch predictor Computing Computer architecture Computer hardware
67	Using Dataflow Based Context for Accurate Value Prediction Renju Thomas ECE Department University of Maryland College Park, MD 20742 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:57 Electronic engineering Computing Microarchitecture Microprocessors Instruction set Central processing unit Computer engineering Computer architecture
68	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Memo NoMay, 1994 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:46 Parallel computing Automatic parallelization Microarchitecture Central processing unit Very long instruction word Cell Supercomputer Program optimization 64-bit Computing Concurrent computing Computer programming
69	Analysis of Multithreaded Architectures for Parallel Computing Rafael H. Saavedra-Barrera David E. Culler Thorsten von Eicken Computer Science Division Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:52 Central processing unit Microprocessors Threads Parallel computing CPU cache Multithreading Microarchitecture Cache Simultaneous multithreading Computing Computer hardware Computer architecture
70	A PROCESSOR ARCHITECTURE Mark R. Thistle Institute for DefenseAnalyses SupercomputingResearchCenter Lanham,Maryland 20706 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:52 Central processing unit Instruction set Microarchitecture Instruction cycle Addressing mode Parallel computing Superscalar Transport triggered architecture Computer architecture Computer engineering Computer hardware

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