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Microarchitecture
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#	Item
281	Design Principles for Tamper-Resistant Smartcard Processors Oliver K¨ommerling Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 1999-05-31 07:23:55 Electronic engineering Microcode Microarchitecture Clock signal Digital signal processor Microcontroller Cell Pirate decryption Joint Test Action Group Computer architecture Central processing unit Computer hardware
282	A Study of Slipstream Processors Zach Purser Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-01-16 18:51:02 Central processing unit Parallel computing Branch predictor CPU cache Re-order buffer Microarchitecture Slipstream Superscalar Simultaneous multithreading Computer architecture Computer hardware Computing
283	. Guest Editor’s Introduction Add to Reading List Source URL: www.ee.ryerson.ca Language: English - Date: 2003-01-27 17:14:38 Central processing unit Microprocessors Classes of computers Instruction set architectures ARM architecture Microarchitecture Instruction set Reduced instruction set computing CPU cache Computer architecture Computer hardware Computing
284	MLP yes! ILP no! Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-10-18 20:47:54 Computing Microprocessors Memory-level parallelism Cache CPU cache Microarchitecture Multithreading MLP Parallel computing Computer architecture Computer hardware Central processing unit
285	Tamper Evident Microprocessors Adam Waksman Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2010-05-27 14:40:04 Computing Computer memory Microprocessors CPU cache Cache Microarchitecture Intel Core Branch predictor Translation lookaside buffer Computer hardware Computer architecture Central processing unit
286	by J. M. Tendler J. S. Dodson J. S. Fields, Jr. Add to Reading List Source URL: www.cc.gatech.edu Language: English - Date: 2005-12-28 21:05:45 Central processing unit Classes of computers POWER4 CPU cache POWER3 Microarchitecture Instruction pipeline IBM POWER Instruction set Computer architecture Computer hardware Computer engineering
287	PDF Document Add to Reading List Source URL: users.ece.utexas.edu Language: English - Date: 2007-05-16 21:35:00 Computer engineering Firmware Assembly languages Microcode Instruction cycle Control store LC-3 Microarchitecture Instruction set Computer architecture Computer hardware Central processing unit
288	PDF Document Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-07-13 17:53:38 Computing Cache CPU cache Computer memory MESI protocol Microarchitecture Computer hardware Central processing unit Computer architecture
289	Microsoft PowerPoint - RISCvsCISC.ppt Add to Reading List Source URL: www.seas.upenn.edu Language: English - Date: 2007-02-19 16:15:50 Central processing unit Classes of computers Instruction set architectures Complex instruction set computing Reduced instruction set computing Instruction set Microarchitecture Microcode Addressing mode Computer architecture Computing Computer engineering
290	PDF Document Add to Reading List Source URL: www.jilp.org Language: English - Date: 2004-01-21 11:48:44 Computer architecture Central processing unit Instruction-level parallelism Data parallelism Microarchitecture Java bytecode Task parallelism Superscalar Thread Computing Computer programming Parallel computing

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