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Microarchitecture
Results: 310

#	Item
141	Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors Marcelo Cintra, Jose´ F. Mart´ınez, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-C Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 12:21:04 Central processing unit Microprocessors CPU cache Cache Computer memory Parallel computing Microarchitecture Memory disambiguation Data structure alignment Computer hardware Computer architecture Computing
142	The Design Complexity of Program Undo Support in a General-Purpose Processor Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-10-16 18:49:08 Central processing unit Cache CPU cache Computer memory Microarchitecture AMD 10h Parallel computing LEON Speculative execution Computer hardware Computer architecture Computer engineering
143	WeeFence: Toward Making Fences Free in TSO ∗ Yuelu Duan, † Abdullah Muzahid, Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-04-25 09:29:13 Computer memory Central processing unit Memory barrier CPU cache Write buffer Parallel computing Cache Compiler optimization Microarchitecture Computer architecture Computing Computer hardware
144	Profile-Based Energy Reduction for High-Performance Processors Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:52:52 Computer architecture Profilers Software optimization CPU cache Cache Computer memory Profiling Program optimization Microarchitecture Computing Computer hardware Central processing unit
145	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
146	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
147	Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-05-11 13:27:29 Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit
148	An Updated Evaluation of ReCycle Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu {atiwari,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:09:56 ReCycle Feedback Reason Microarchitecture Pipeline Recycling Computer architecture Computer hardware Electronic engineering
149	Software Logging under Speculative Parallelization ´ Garzar´an, Milos Prvulovicy , Jos´e Mar´ıa Llaber´ıaz , Mar´ıa Jesus ˜ V´ıctor Vinals, Lawrence Rauchwergerx , and Josep Torrellasy Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-09-30 19:59:18 Central processing unit Parallel computing Microprocessors Computer memory CPU cache Microarchitecture Cache Automatic parallelization Superscalar Computer hardware Computer architecture Computing
150	SWICH: A PROTOTYPE FOR EFFICIENT CACHE-LEVEL CHECKPOINTING AND ROLLBACK EXISTING CACHE-LEVEL CHECKPOINTING SCHEMES DO NOT CONTINUOUSLY SUPPORT A LARGE ROLLBACK WINDOW. IMMEDIATELY AFTER A CHECKPOINT, THE NUMBER OF INSTRU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-05-03 11:36:50 Computer memory Computer engineering Cache Application checkpointing CPU cache Microarchitecture SPARC64 Memory hierarchy Runahead Computer hardware Computer architecture Central processing unit

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