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Microarchitecture
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#	Item
91	Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow Wilson W. L. Fung Ivan Sham George Yuan Tor M. Aamodt Department of Electrical and Computer Engineering Add to Reading List Source URL: www.ece.ubc.ca Language: English - Date: 2007-09-25 22:46:38 Parallel computing Computer architecture Microprocessors Central processing unit GPGPU Stream processing Multithreading Microarchitecture SIMD Computing Computer hardware Concurrent computing
92	Vector IRAM: ISA and Micro-architecture Christoforos E. Kozyrakis Computer Science Division University of California, Berkeley Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 1998-08-24 18:37:00 Computer engineering Vector processor Instruction set Vector Computer Microarchitecture The Berkeley IRAM Project Central processing unit Computer architecture Computing
93	Microarchitecture Studies of the Human Multifidus Muscle Reveal its Unique Design as a Major Dynamic Stabilizer of the Lumbar Spine Add to Reading List Source URL: muscle.ucsd.edu Language: English - Date: 2008-02-25 18:40:18 Multifidus muscle Muscle Human back Lumbar Back Flexion Anatomy Muscles of the torso Muscular system
94	Prefetching and Cache Management Using Task Lifetimes Vassilis Papaefstathiou∗ Manolis G.H. Katevenis∗ FORTH-ICS Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 04:38:59 Computer memory Cache Central processing unit Microprocessors CPU cache Prefetcher Multi-core processor Microarchitecture X86 Computer hardware Computing Computer architecture
95	MEMORY HIERARCHY DESIGN FOR STREAM COMPUTING A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:06 Microprocessors GPGPU Central processing unit Stream processing Parallel computing Cell Microarchitecture Granularity Stream Processors Inc Computer architecture Computing Computer engineering
96	SYNERGISTIC CACHING IN SINGLE-CHIP MULTIPROCESSORS a dissertation submitted to the department of electrical engineering and the committee on graduate studies Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Cache Computer architecture Central processing unit Computer engineering Microprocessors CPU cache Microarchitecture Computer memory Computer hardware Computing
97	MEMORY AND CONTROL ORGANIZATIONS OF STREAM PROCESSORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2009-11-09 11:38:32 Computer engineering GPGPU Stream processing Microprocessors Parallel computing Dynamic random-access memory Microarchitecture Central processing unit Computing Computer architecture Computer hardware
98	Department of Electrical and Computer Systems Engineering Technical Report MECSE Add to Reading List Source URL: www.ecse.monash.edu.au Language: English - Date: 2006-06-18 18:17:24 Central processing unit Classes of computers Microprocessors Parallel computing Dataflow architecture Instruction set Cell Microarchitecture Superscalar Computer architecture Computer engineering Computer hardware
99	Epiphany Architecture Reference Table of Contents 1 Introduction ......................................................................................................................... 10 Add to Reading List Source URL: www.adapteva.com Language: English - Date: 2014-03-11 18:06:17 Computing Direct memory access Control register Interrupt Processor register Microarchitecture Computer hardware Computer architecture Central processing unit
100	How the SPARC T4 Processor Optimizes Throughput Capacity: A Case Study Add to Reading List Source URL: www.oracle.com Language: English Microprocessors Threads UltraSPARC T2 Microarchitecture UltraSPARC SPARC T4 CPU cache NOP Instruction set Computer hardware Computer architecture Central processing unit

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