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Memory ordering
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#	Item
1	The Semantics of x86-CC Multiprocessor Machine Code Susmit Sarkar1 Scott Owens1 Tom Ridge1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:01 Computing Computer architecture Software engineering X86 architecture Computer memory Low-level programming language Spinlock X86 Assembly language Memory barrier Memory ordering Exit
2	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-10-12 15:57:01 Computing Computer architecture Computer memory Transaction processing Concurrency Cache coherency MESI protocol Memory ordering Consistency model Cache coherence Linearizability Memory barrier
3	PDF Document Add to Reading List Source URL: tomcoughlin.com Language: English - Date: 2010-02-22 03:14:13 Electromagnetism Computer hardware Spintronics Non-volatile memory Emerging technologies Magnetic ordering Magnetoresistive random-access memory Magnet Fax Ferromagnetism Computer data storage
4	Design of Parallel and High-Performance Computing Fall 2013 Lecture: Linearizability Instructor: Torsten Hoefler & Markus Püschel Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-10-26 16:22:37 Computing Computer architecture Software engineering Computer memory Transaction processing Concurrency Compiler construction Linearizability Memory ordering Consistency model Cache coherence Sequential consistency
5	High-Performance Concurrency Control Mechanisms for Main-Memory Databases Add to Reading List Source URL: web.cse.ohio-state.edu Language: English - Date: 2015-08-14 19:41:22 Transaction processing Computing Data management Data Concurrency control Databases Serializability Isolation Optimistic concurrency control Snapshot isolation Global serializability Commitment ordering
6	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-11-03 08:27:59 Computer memory Transaction processing Parallel computing Compiler construction Concurrency Cache coherence Memory ordering Consistency model Linearizability Sequential consistency CPU cache Processor consistency
7	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-04 17:36:16 Computer memory Transaction processing Computer architecture Concurrency control Compiler construction Memory ordering Consistency model Cache coherence Memory barrier Linearizability Schedule Sequential consistency
8	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Instruction set architectures Computer memory X86 architecture X86-64 Java memory model X86 Memory barrier Spinlock Memory ordering Low-level programming language Itanium ARM architecture
9	GASPI proposal: Memory Ordering Olaf Krzikalla Technische Universit¨at, Dresden, Germany, July 3, 2015 Add to Reading List Source URL: www.gaspi.de Language: English - Date: 2016-06-01 06:47:00