Linearizability

Results: 416



#Item
41Review of last lecture  Cache-coherence is not enough!  Many more subtle issues for parallel programs!

Review of last lecture  Cache-coherence is not enough!  Many more subtle issues for parallel programs!

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Source URL: spcl.inf.ethz.ch

Language: English - Date: 2013-10-13 13:49:30
42Making RAMCloud Writes Even Faster (Bring Asynchrony to Distributed Systems) Seo Jin Park John Ousterhout

Making RAMCloud Writes Even Faster (Bring Asynchrony to Distributed Systems) Seo Jin Park John Ousterhout

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Source URL: stanford.edu

Language: English - Date: 2016-06-10 01:40:17
43High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah)

High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah)

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Source URL: hpts.ws

Language: English - Date: 2015-10-02 08:07:40
44A Constructive Approach for Proving Data Structures’ Linearizability ?  Kfir Lev-Ari1 , Gregory Chockler2 , and Idit Keidar1

A Constructive Approach for Proving Data Structures’ Linearizability ? Kfir Lev-Ari1 , Gregory Chockler2 , and Idit Keidar1

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Source URL: webee.technion.ac.il

Language: English - Date: 2015-08-17 06:31:40
45Administrivia  Design of Parallel and High-Performance Computing Fall 2013

Administrivia  Design of Parallel and High-Performance Computing Fall 2013

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Source URL: spcl.inf.ethz.ch

Language: English - Date: 2014-11-30 16:07:53
46What is Safe in Transactional Memory Hagit Attiya1 Sandeep Hans1  Petr Kuznetsov2

What is Safe in Transactional Memory Hagit Attiya1 Sandeep Hans1 Petr Kuznetsov2

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Source URL: rp-www.cs.usyd.edu.au

Language: English - Date: 2012-07-13 04:06:54
47Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

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Source URL: spcl.inf.ethz.ch

Language: English - Date: 2013-11-03 08:27:59
48Design of Parallel and High-Performance Computing Fall 2013 Lecture: Languages and Locks  Instructor: Torsten Hoefler & Markus Püschel

Design of Parallel and High-Performance Computing Fall 2013 Lecture: Languages and Locks Instructor: Torsten Hoefler & Markus Püschel

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Source URL: spcl.inf.ethz.ch

Language: English - Date: 2014-10-26 16:22:37
49Lock-free Dynamically Resizable Arrays Damian Dechev, Peter Pirkelbauer, and Bjarne Stroustrup Texas A&M University College Station, TX {dechev, peter.pirkelbauer}@tamu.edu,

Lock-free Dynamically Resizable Arrays Damian Dechev, Peter Pirkelbauer, and Bjarne Stroustrup Texas A&M University College Station, TX {dechev, peter.pirkelbauer}@tamu.edu,

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Source URL: pirkelbauer.com

Language: English - Date: 2011-11-03 23:35:23
50Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

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Source URL: spcl.inf.ethz.ch

Language: English - Date: 2015-10-04 17:36:16