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Formal equivalence checking / Integrated circuit design / Application-specific integrated circuit / Logic synthesis / Place and route / Register-transfer level / High-level synthesis / Netlist / Wire wrap / Electronic engineering / Electronic design automation / Engineering Change Order
Date: 2004-03-21 14:53:16
Formal equivalence checking
Integrated circuit design
Application-specific integrated circuit
Logic synthesis
Place and route
Register-transfer level
High-level synthesis
Netlist
Wire wrap
Electronic engineering
Electronic design automation
Engineering Change Order

The Human ECO Compiler Steve Golson

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