Hardware verification languages - Document - PDFSEARCH.IO

First Page		Document Content
Date: 2011-04-14 06:00:26 Electronic design Hardware verification languages SystemC Verilog Register-transfer level High-level synthesis Logic synthesis VHDL Integrated circuit design Electronic engineering Electronic design automation Hardware description languages		Add to Reading List Source URL: www.cl.cam.ac.uk Download Document from Source Website File Size: 3,85 MB Share Document on Facebook

	Dissertation Reactive Synthesis: branching logic & parameteri zed systems Ayrat Khalimov Advisor: Roderick Bloem DocID: 1xVvj - View Document
	Synthesis of Logic Interpretations Jian Xiang, John Knight, Kevin Sullivan Department of Computer Science University of Virginia Charlottesville, VA USA {Jian,Knight,Sullivan}@cs.virginia.edu DocID: 1vpwF - View Document
	Reactive Synthesis from Signal Temporal Logic Specifications Vasumathi Raman Alexandre Donzé DocID: 1uiFq - View Document
	Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks W. B. Toms, D. A. Edwards School of Computer Science, University of Manchester {tomsw,doug}@cs.man.ac.uk DocID: 1u5OA - View Document
	Switching Logic Synthesis for Reachability∗ Ankur Taly Ashish Tiwari Computer Science Dept., Stanford University DocID: 1t1e9 - View Document