<--- Back to Details
First PageDocument Content
Application programming interfaces / Computer architecture / Message Passing Interface / Graphics hardware / Multi-core processor / Coprocessor / Embedded system / Computer cluster / Hardware acceleration / Computing / Parallel computing / Central processing unit
Date: 2013-07-28 00:11:23
Application programming interfaces
Computer architecture
Message Passing Interface
Graphics hardware
Multi-core processor
Coprocessor
Embedded system
Computer cluster
Hardware acceleration
Computing
Parallel computing
Central processing unit

Programming the Nallatech Xeon + Multi-FPGA Platform

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 406,52 KB

Share Document on Facebook

Similar Documents

Graph theory / Mathematics / Discrete mathematics / Graph traversal / Graph / Directed graph / Breadth-first search / Degree / Line graph / Clique

Language and Hardware Acceleration Backend for Graph Processing Andrey Mokhov† , Alessandro de Gennaro† , Ghaith Tarawneh† , Jonny Wray‡ , Georgy Lukyanov† , Sergey Mileiko† , Joe Scott† , Alex Yakovlev†

DocID: 1xUEl - View Document

Hardware Acceleration for Programs in SSA Form

DocID: 1upt7 - View Document

Reconfigurable Hardware Acceleration of Canonical Graph Labelling David B. Thomas1 , Wayne Luk1 , Michael Stumpf2 1 2

DocID: 1sQhm - View Document

Exar Highlights Enhanced Hadoop Economics and Performance Using Hardware Acceleration at Open Server Summit FREMONT, Calif., Nov. 12, 2014 /PRNewswire/ -- Exar Corporation (NYSE: EXAR), a leading supplier of high-perform

DocID: 1rwbv - View Document

Computing / Networking hardware / Intel Corporation / Tarari / Content processor / Hardware acceleration

The T9000 Family of Content Processor ASICs

DocID: 1qBzN - View Document