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Delay insensitive circuit
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#	Item
1	Microsoft PowerPoint - 21_lines [Read-Only] Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:40:39 Computer hardware Synchronization Clock signal Central processing unit Delay insensitive circuit Asynchrony Flip-flop Clock gating Pipeline Electronic engineering Electronics Digital electronics
2	Terabit Clockless Crossbar Switch in 130nm Uri Cummings [removed] 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:42:32 Electrical engineering Electrical circuits Asynchronous circuit Clock signal Central processing unit Flip-flop Dynamic logic Delay insensitive circuit Logic family Electronic engineering Digital electronics Electronics
3	TITAC–2: A 32-bit Scalable-Delay-Insensitive Microprocessor Takashi Nanya1) 2) Akihiro Takamura2), Masashi Kuwako1), Masashi Imai1) Taro Fujii2), Motokazu Ozawa2), Izumi Fukasaku2), Yoichiro Ueno2) Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:03 Electrical circuits Electronics Quasi Delay Insensitive Synchronization Delay insensitive circuit Flip-flop Clock signal Futures and promises Combinational logic Electronic engineering Digital electronics Electrical engineering
4	25 YEARS AGO: THE FIRST ASYNCHRONOUS MICROPROCESSOR Alain J. Martin Department of Computer Science California Institute of Technology Pasadena, CA 91125, USA Add to Reading List Source URL: authors.library.caltech.edu Language: English - Date: 2014-02-06 14:24:49 Computer hardware Central processing unit Telecommunications engineering Quasi Delay Insensitive Microprocessors Asynchronous circuit CPU design Datapath Reduced instruction set computing Electronic engineering Electrical circuits Electrical engineering
5	INVITED PAPER Asynchronous Techniques for System-on-Chip Design Digital circuit designs that are not sensitive to delay promise to allow operation Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2006-12-08 14:20:39 Electrical engineering Telecommunications engineering Communication Network performance Data transmission Quasi Delay Insensitive Delay insensitive circuit Asynchronous circuit Asynchronous system Electronic engineering Electrical circuits Synchronization
6	Asynchronous Nano-electronics: Preliminary Investigation Alain J. Martin & Piyush Prakash Department of Computer Science California Institute of Technology Pasadena, CA 91125, USA Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2008-04-28 21:17:16 Electrical circuits Digital electronics Integrated circuits Logic gates Logic families Quasi Delay Insensitive CMOS Asynchronous circuit Transistor Electronic engineering Electrical engineering Electronics
7	Soft-error Mitigation for Asynchronous FPGAs Wonjin Jang, Alain J. Martin Computer Science Department California Institute of Technology Pasadena, CA[removed]Abstract— This paper addresses the issue of soft errors in Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2006-12-08 14:20:39 Field-programmable gate array Electronic design automation Fabless semiconductor companies Soft error Quasi Delay Insensitive Asynchronous circuit Programmable logic device Actel Application-specific integrated circuit Electronic engineering Electrical circuits Digital electronics
8	25 YEARS AGO: THE FIRST ASYNCHRONOUS MICROPROCESSOR Alain J. Martin Department of Computer Science California Institute of Technology Pasadena, CA 91125, USA Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2014-01-28 17:16:01 Computer hardware Central processing unit Telecommunications engineering Quasi Delay Insensitive Microprocessors Asynchronous circuit CPU design Datapath Reduced instruction set computing Electronic engineering Electrical circuits Electrical engineering
9	Soft-error Robustness in QDI Circuits Wonjin Jang, Alain J. Martin Computer Science Department California Institute of Technology Pasadena, CA[removed]Abstract Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2006-12-08 14:20:39 Digital electronics Variables Algebraic logic Quasi Delay Insensitive Soft error Final Circuit Hazard Boolean algebra Computing Mathematics Software engineering
10	1 Three Generations of Asynchronous Microprocessors Alain J. Martin, Mika Nystr¨om, Catherine G. Wong Department of Computer Science Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2003-08-13 19:45:22 Electrical circuits Instruction set architectures MIPS architecture Asynchronous circuit R4000 Quasi Delay Insensitive R4600 Alpha 21064 Central processing unit Computer architecture Electronic engineering Computer hardware

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