Coprocessors

Results: 17



#Item
1An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors Jack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb+ , Vikram Bhatt, Steven Swanson, and M

An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors Jack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb+ , Vikram Bhatt, Steven Swanson, and M

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Source URL: cseweb.ucsd.edu

- Date: 2011-08-22 21:37:18
    2MVAPICH2-MIC on Beacon: Exploring Performance on a Cluster with 4 Coprocessors per

    MVAPICH2-MIC on Beacon: Exploring Performance on a Cluster with 4 Coprocessors per

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    Source URL: mug.mvapich.cse.ohio-state.edu

    - Date: 2015-11-20 13:17:46
      3Tera-Scale 1D FFT with Low-Communication Algorithm and Intel Xeon Phi Coprocessors R TM

      Tera-Scale 1D FFT with Low-Communication Algorithm and Intel Xeon Phi Coprocessors R TM

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      Source URL: pcl.intel-research.net

      Language: English - Date: 2014-12-03 02:39:18
        4Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training One-day Seminar  CDT 101

        Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training One-day Seminar CDT 101

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        Source URL: www.colfax-intl.com

        Language: English - Date: 2015-06-01 03:04:00
          5Scientific Computing with Intel Xeon Phi Coprocessors Andrey Vladimirov Colfax International HPC Advisory Council Stanford Conference 2015 Compututing with Xeon Phi

          Scientific Computing with Intel Xeon Phi Coprocessors Andrey Vladimirov Colfax International HPC Advisory Council Stanford Conference 2015 Compututing with Xeon Phi

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          Source URL: hpcadvisorycouncil.com

          Language: English - Date: 2015-02-02 12:20:22
            6Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training Four-day Workshop  CDT 401

            Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training Four-day Workshop CDT 401

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            Source URL: www.colfax-intl.com

            Language: English - Date: 2015-06-01 03:04:00
            7Development Case Study Intel® C++ Composer XE Realtime superresolution program Intel® C++ Composer XE and Intel® Xeon Phi™ Coprocessors:

            Development Case Study Intel® C++ Composer XE Realtime superresolution program Intel® C++ Composer XE and Intel® Xeon Phi™ Coprocessors:

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            Source URL: software.intel.com

            Language: English - Date: 2013-04-01 11:52:19
              8On the Design, Development, and Analysis of Optimized Matrix-Vector Multiplication Routines for Coprocessors Khairul Kabir1 , Azzam Haidar1 , Stanimire Tomov1 , and Jack Dongarra1,2,3 1 2

              On the Design, Development, and Analysis of Optimized Matrix-Vector Multiplication Routines for Coprocessors Khairul Kabir1 , Azzam Haidar1 , Stanimire Tomov1 , and Jack Dongarra1,2,3 1 2

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              Source URL: icl.cs.utk.edu

              Language: English - Date: 2015-03-23 16:54:43
                9Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training One-day Boot Camp  Abstract: Colfax Developer Training (CDT) is an in-depth intensive

                Programming and Optimization with Intel Xeon Phi Coprocessors Colfax Developer Training One-day Boot Camp Abstract: Colfax Developer Training (CDT) is an in-depth intensive

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                Source URL: www.colfax-intl.com

                Language: English - Date: 2015-01-13 00:36:00
                  10Practical server privacy with secure coprocessors by S. W. Smith D. Safford

                  Practical server privacy with secure coprocessors by S. W. Smith D. Safford

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                  Source URL: www.cs.dartmouth.edu

                  Language: English - Date: 2005-08-18 17:48:27