Brayton

Results: 169



#Item
21Formal methods / Mathematics / Network flow / Retiming / Electronic design automation / Electronic design / Maximum flow problem / Design closure / Clock skew / Electronic engineering / Operations research / Electronics

1 Scalable Min-Register Retiming Under Timing and Initializability Constraints Aaron P. Hurst, Alan Mishchenko, and Robert K. Brayton University of California, Berkeley

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Source URL: www.bvsrc.org

Language: English - Date: 2008-04-03 12:04:29
22Boolean network / American International Group / Science / Economy of New York City / Electronics / Diagrams / And-inverter graph / Electronic design automation

Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 19:34:13
23Digital electronics / Diagrams / Logic in computer science / And-inverter graph / Retiming / Logic synthesis / Formal verification / Combinational logic / Standard cell / Electronic engineering / Electronic design automation / Formal methods

Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 19:34:23
24Logic in computer science / Mathematics / Formal methods / Computer memory / Binary trees / Retiming / Flip-flop / Sequential logic / Combinational logic / Theoretical computer science / Digital electronics / Electronic engineering

Sequential Rewriting and Synthesis Robert Brayton Alan Mishchenko EECS Department, University of California, Berkeley, CA 94720

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Source URL: www.bvsrc.org

Language: English - Date: 2007-04-23 21:49:16
25Boolean network / Canonical form / Artificial neuron / Science / Abstraction / Logic / Neural networks / Bioinformatics

A Theory of Non-Deterministic Networks Alan Mishchenko and Robert K. Brayton Department of EECS, University of California at Berkeley {alanmi, brayton}@eecs.berkeley.edu Abstract

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Source URL: www.bvsrc.org

Language: English - Date: 2003-08-12 19:40:51
26Digital electronics / Electronic design / Formal methods / And-inverter graph / Retiming / Logic synthesis / Automatic test pattern generation / Field-programmable gate array / Sequential logic / Electronic engineering / Electronics / Electronic design automation

Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton

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Source URL: www.bvsrc.org

Language: English - Date: 2006-05-01 16:05:11
27Electronics / Boolean algebra / Diagrams / Algebraic logic / And-inverter graph / Logic synthesis / Boolean function / Circuit / Topology / Electronic engineering / Electromagnetism / Electronic design automation

Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2005-05-01 15:18:03
28Electronics / Diagrams / Boolean algebra / And-inverter graph / Canonical form / Logic synthesis / Circuit / Boolean function / Topology / Electronic engineering / Electromagnetism / Electronic design automation

Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS

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Source URL: www.bvsrc.org

Language: English - Date: 2006-02-27 20:55:14
29Binary trees / Applied mathematics / R-tree / Dynamic programming / Equations / Systems engineering / B-tree / Linear programming / Tango tree / Mathematics / Operations research / Graph theory

A Linear Time Algorithm for Optimum Tree Placement Satrajit Chatterjee Zile Wei Alan Mishchenko Robert Brayton Department of EECS U. C. Berkeley {satrajit, zile, alanmi, brayton}@eecs.berkeley.edu

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Source URL: www.bvsrc.org

Language: English - Date: 2007-04-23 22:39:34
30Latin alphabets

Composition Operators in Language Equations Nina Yevtushenko¶ Tiziano Villa§,† Robert K. Brayton‡

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Source URL: www.bvsrc.org

Language: English - Date: 2004-04-29 17:59:32
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