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Atomic swap
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1	Atomics in UPC A memory operation is atomic in case the only observable states for the memory are the state before the operation began or the state after the operation has completed. It is as if the operation happens at Add to Reading List Source URL: upc.gwu.edu Language: English - Date: 2013-12-04 13:04:31 Data management Compare-and-swap Pointer Linearizability Swap Lock Ctrie Concurrency control Computing Computer programming
2	Atomic increments Enrique Soriano−Salvador Laboratorio de Sistemas Universidad Rey Juan Carlos Gorka Guardiola Múzquiz Add to Reading List Source URL: lsub.org Language: English - Date: 2014-05-08 10:53:18 Concurrency Spinlock Fetch-and-add MOV Test-and-set Lock X86-64 Compare-and-swap Non-blocking algorithm Concurrency control Computer architecture Computing
3	Atomic Instructions in Java David Hovemeyer, William Pugh, and Jaime Spacco Dept. of Computer Science, University of Maryland, College Park, MDUSA {daveho,pugh,jspacco}@cs.umd.edu Abstract. Atomic instructions at Add to Reading List Source URL: faculty.ycp.edu Language: English - Date: 2014-08-22 12:24:21 Concurrency Compare-and-swap Linearizability Double compare-and-swap Lock Load-link/store-conditional Non-blocking algorithm Memory barrier Monitor Concurrency control Computing Computer architecture
4	Fourth Workshop on Scalable Shared Memory Multiprocessors, Chicago, IL, April 1994 Scalable Atomic Primitives for Distributed Shared Memory Multiprocessors (Extended Abstract) Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 18:54:48 Concurrency Compare-and-swap Linearizability Non-blocking algorithm Test-and-set Load-link/store-conditional CPU cache Parallel computing Transactional memory Concurrency control Computing Computer architecture
5	Tech. Rep[removed]Scalability of Atomic Primitives on Distributed Shared Memory Multiprocessors Maged M. Michael Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 21:03:43 Compare-and-swap Linearizability Test-and-set Fetch-and-add Non-blocking algorithm CPU cache Spinlock Parallel computing Instruction set Concurrency control Computing Computer architecture

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