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#	Item
591	Tips and Techniques for 28-nm Design Optimization WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2011-11-01 17:56:19 Clock signal Field-programmable gate array Fabless semiconductor companies Altera Clock skew Design closure Timing closure Phase-locked loop Conventional PCI Electronic engineering Electronics Electronic design
592	Optimizing Nios II C2H Compiler Results Add to Reading List Source URL: www.altera.com Language: English - Date: 2011-07-21 22:15:49 Programming language implementation Computer performance Compiler optimizations Software optimization Nios II Procedural programming languages Compiler Inline expansion Program optimization Computing Software engineering Computer programming
593	Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA[removed]www.altera.com Add to Reading List Source URL: www.altera.com Language: English - Date: 2014-03-18 23:15:37 Electronic engineering Structure Altera Datasheet Technology
594	Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-02-07 18:21:05 PCI Express Altera Field-programmable gate array Nehalem Nvidia Ion DDR3 SDRAM AMD 700 chipset series PowerPC 400 Computer hardware Computer buses Electronic engineering
595	User-Customizable ARM-Based SoCs for Next-Generation Embedded Systems WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-06-27 04:22:32 Fabless semiconductor companies Electronic design Instruction set architectures ARM architecture Altera Field-programmable gate array Soft microprocessor Embedded system Advanced Microcontroller Bus Architecture Electronic engineering Computer architecture Electronics
596	Lei n.º 53-D/2006 de 29 de Dezembro Altera a contribuição dos beneficiários dos subsistemas de saúde da Administração Pública A Assembleia da República decreta, nos termos da alínea c) do artigo 161.º da Const Add to Reading List Source URL: www.dgaep.gov.pt Language: Portuguese - Date: 2008-02-06 05:33:00
597	Achieving Lowest System Power with Low-Power 28-nm FPGAs WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2012-03-26 14:59:00 Altera Field-programmable gate array Application-specific integrated circuit DDR3 SDRAM Synchronous dynamic random-access memory SiliconBlue Technologies Actel Electronic engineering Fabless semiconductor companies Electronics
598	Implementing Digital Processing for Automotive Radar Using SoCs WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-12-11 04:30:06 Telecommunications engineering Pulse-Doppler radar Doppler radar FMCW Doppler effect Pulse-Doppler signal processing Radar engineering details Radar Technology Wireless
599	FPGA-Adaptive Software Debug and Performance Analysis WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-05-20 22:21:02 Field-programmable gate array Joint Test Action Group Altera Embedded system Advanced Microcontroller Bus Architecture Semiconductor intellectual property core Nios II Xilinx Electronic engineering Electronics Fabless semiconductor companies
600	Optimize Motor Control Designs with an Integrated FPGA Design Flow WP[removed]White Paper Add to Reading List Source URL: www.altera.com Language: English - Date: 2012-05-24 18:09:30 Fabless semiconductor companies Digital electronics Nios II Altera Field-programmable gate array Logic design Sopc builder System on a chip Simulink Electronic engineering Electronics Electronic design

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