XAUI - PDFSEARCH.IO - Document Search Engine

XAUI
Results: 24

#	Item
11	High-speed PHY interface proposal S800BASE-T Study Group Oxford, UK July 8, 2003 Add to Reading List Source URL: grouper.ieee.org Language: English - Date: 2003-07-22 19:02:42 Computer hardware XAUI PHY 10 Gigabit Ethernet IEEE Media Independent Interface OSI protocols Ethernet Computing
12	Cyclone V Device Handbook Volume 2: Transceivers Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-10-17 23:33:50 Ethernet Networking hardware Computer buses Transceiver Altera PCI Express Field-programmable gate array XAUI OBSAI Electronic engineering Electronics Computer hardware
13	Transceiver Protocol Configurations in Cyclone V Devices Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-10-17 23:34:01 PCI Express OSI protocols Nvidia SerDes Nvidia Ion XAUI Computer hardware Computer buses Standards organizations
14	Altera Transceiver PHY IP Core User Guide Add to Reading List Source URL: www.altera.com Language: English - Date: 2014-04-28 20:39:08 10 Gigabit Ethernet PHY PCI Express Altera Ethernet OSI protocols XAUI
15	2. Cyclone IV Reset Control and Power Down May 2013 CYIV[removed]CYIV[removed] Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-05-30 21:49:49 Radio electronics Radar Ethernet Radio-frequency identification Transponder Wireless Transceiver Phase-locked loop XAUI Electronic engineering Electronics Telecommunications engineering
16	1. Cyclone IV Transceivers Architecture October 2013 CYIV[removed]CYIV[removed]Cyclone® IV GX devices include up to eight full-duplex transceivers at serial data Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-10-10 18:08:31 Computer buses Standards organizations Ethernet SerDes Field-programmable gate array XAUI 8b/10b encoding Altera PCI Express Computer hardware Electronic engineering Electronics
17	High Bandwidth, Low Power, and Low BER Altera’s 28-nm, Power-Efficient Transceivers Altera® transceivers have a proven track record of meeting system bandwidth, power, and bit-error rate (BER) requirements. This tech Add to Reading List Source URL: www.altera.com Language: English - Date: 2013-01-24 16:19:18 Technology Ethernet Altera XAUI Field-programmable gate array Jitter Interlaken SerDes Framer Interface QSFP Electronics Electronic engineering Networking hardware
18	NP[removed]Gigabit Network Processor for Carrier Ethernet Applications Add to Reading List Source URL: www.ezchip.com Language: English - Date: 2011-04-14 10:23:42 Network architecture XFP transceiver Packet Processing XAUI Network processor 10 Gigabit Ethernet Interlaken SerDes 100 Gigabit Ethernet Ethernet OSI protocols Electronic engineering
19	Stratix II GX Device Handbook: Stratix II GX Architecture Add to Reading List Source URL: www.altera.com Language: English - Date: 2007-10-02 12:40:10 Computer buses SerDes XAUI Altera Transceiver Universal asynchronous receiver/transmitter Phase-locked loop Field-programmable gate array PCI Express Electronic engineering Electronics Ethernet
20	Chapter 2: Arria GX Architecture Add to Reading List Source URL: www.altera.com Language: English - Date: 2009-11-30 21:55:49 Computer hardware SerDes XAUI Phase-locked loop Universal asynchronous receiver/transmitter Low-voltage differential signaling Transceiver PCI Express Altera Electronic engineering Electronics Computer buses

UPDATE