Validation of Systems−on−a−Chip at the Transactional Level STMicroelectronics UJF−VERIMAG Common Lab openTLM : a Minalogic project UJF−VERIMAG Synchrone STMicroelectronics HPC SPG Group - Transaction-level modeling - Document - PDFSEARCH.IO

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	Validation of Systems−on−a−Chip at the Transactional Level STMicroelectronics/UJF−VERIMAG Common Lab openTLM : a Minalogic project UJF−VERIMAG / Synchrone STMicroelectronics HPC / SPG Group Add to Reading List Document Date: 2009-07-17 12:28:13 Open Document File Size: 1,52 MB Share Result on Facebook Company nuSMV Verification Tools PVT / SPG Group Systems / RTL / Embedded Software / / Event M&A / / IndustryTerm simulation tool / / Position Non−Preemptive Scheduler / Programmer / / ProgrammingLanguage C++ / / Technology simulation / / SocialTag Logic design SystemC Logic simulation Transaction-level modeling Electronic engineering Digital electronics Electronic design automation

Validation of Systems−on−a−Chip at the Transactional Level STMicroelectronics/UJF−VERIMAG Common Lab openTLM : a Minalogic project UJF−VERIMAG / Synchrone STMicroelectronics HPC / SPG GroupAdd to Reading List