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Electronic design automation / SystemC / Logic design / Transaction-level modeling / High-level synthesis / VHDL / Advanced Learning and Research Institute / Verilog / Catapult C / Electronic engineering / Hardware description languages / Digital electronics


LusSy: an open Tool for the Analysis of Systems-on-aChip at the Transaction Level Matthieu Moy∗ , Florence Maraninchi* , Laurent Maillet-Contoz† Abstract. We describe a toolbox for the analysis of Systems-on-a-chip w
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Document Date: 2007-12-17 11:12:12

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File Size: 416,69 KB

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Company

ARM Limited / Texas Instruments / RTL / Philips / System Platform Group / STMicroelectronics / Intel / /

Country

France / Netherlands / /

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Facility

SystemC library / port Figure / /

IndustryTerm

tool chain / software model-checking techniques / software parts / visualization tools / embedded software development / formal verification tools / software model-checking tools / interactive visualization tool / verification tools / embedded software / heterogeneous hardware/software systems / software descriptions / dedicated tool / synchronous and asynchronous communication protocols / open and other tools / /

Organization

US Federal Reserve / Centre ´equation / /

Person

Laurent Maillet-Contoz / Florence Maraninchi / /

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Position

netlist extractor / representative / scheduler / Back-end Independent Semantic Extractor / SystemC scheduler / /

Product

Pinapa / /

ProgrammingLanguage

Verilog / C++ / /

Technology

Verilog / Java / perl / simulation / operating system / PROVER Technology / synchronous and asynchronous communication protocols / VHDL / network protocols / /

SocialTag