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Torrellas
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#	Item
101	Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas Department of Computer Science University o Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 17:56:46 Human behavior Motivation VisIt Behavior Application software Vladimiro Montesinos Software Cognition Experimental psychology
102	ReCycle: Pipeline Adaptation to Tolerate Process Variation∗ Abhishek Tiwari, Smruti R. Sarangi and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-11 01:31:00 Electronic engineering Central processing unit Pipeline Hazard Clock distribution network Clock skew Alpha 21264 CPU cache Computer architecture Computer hardware Clock signal
103	BulkCommit: Scalable and Fast Commit of Atomic Blocks in a Lazy Multiprocessor Environment Xuehai Qian, Benjamin Sahelices Josep Torrellas, Depei Qian Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-02-19 00:20:13 Cache Central processing unit Computer memory C dynamic memory allocation Computer architecture Computer hardware Computing CPU cache
104	Volition: Scalable and Precise Sequential Consistency Violation Detection Xuehai Qian, Josep Torrellas Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:41 Cache Central processing unit Parallel computing Computing Volition Computer memory Computer hardware CPU cache
105	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware∗ Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas University of Illinois at Urbana-Champaign {sarangi,atiwari,tor Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:11:09 Microprocessors Central processing unit X86 architecture Multi-core processor Parallel computing Athlon CPU cache P5 Microcode Computer hardware Computer architecture Computing
106	The Design Complexity of Program Undo Support in a General Purpose Processor Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 18:05:40 Computing CPU cache Undo Speculative execution Application checkpointing Rollback Speculative Processor register Computer architecture Computer hardware Central processing unit
107	Estimating Design Time for System Circuits Cyrus Bazeghi Francisco J. Mesa-Mart´ınez Brian Greskamp† Josep Torrellas† Jose Renau Dept. of Computer Engineering, University of California Santa Cruz http://masc.soe.uc Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-02-28 21:02:12 Electronics manufacturing Electronic design Integrated circuits Electrical engineering Printed circuit board Routing Integrated circuit design Surface-mount technology PCB Electronic engineering Electronics Electromagnetism
108	Microsoft PowerPoint - present_isca11_2 Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-06-30 12:31:41 Josep Torrellas Computer architecture Honda P series CPU cache Application checkpointing Computing Computer hardware
109	Prototyping Architectural Support for Program Rollback Using FPGAs Radu Teodorescu Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 18:05:04 Electronics Computing Xilinx Field-programmable gate array VHDL Embedded systems Electronic engineering Reconfigurable computing Fabless semiconductor companies
110	Microsoft PowerPoint - present_ics05_1 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-25 19:24:42 Strauss Sarangi Computing Sound Music Concurrent computing Josep Torrellas Thread

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