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Electronic engineering / Computer architecture / Parallel computing / Scratchpad memory / CPU cache / Remote direct memory access / Multi-core processor / Network On Chip / Throughput / Computing / Computer memory / Computer hardware


Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Xiaojun Yang, Stamatis Kavadias, Manolis Katevenis Institute of Comp
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Document Date: 2013-12-23 07:16:58


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City

Crete / /

Company

Xilinx / /

Country

Greece / /

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Facility

Eindhoven University of Technology / Manolis Katevenis Institute of Computer Science / /

IndustryTerm

off-chip interconnection network / iterative matching algorithms / software configuration / interconnection network / iSLIP scheduling algorithm / real-time applications / sequential iterative matching algorithm / local area networks / multiprocessor systems / software notification / multicore systems / /

Organization

US Federal Reserve / Foundation for Research and Technology / European Union / International Criminal Court / Manolis Katevenis Institute of Computer Science / Eindhoven University of Technology / /

Person

Nick McKeown / Jonathan Chao / George Kalokerinos / Johan Agnes Minkenberg / Deng Pan / H. Jonathan Chao / George Nikiforos / /

Position

cache controller / request arbiter / grant arbiter / General / producer / transmitting controller / arbiter / grant arbiter / and so on / /

ProgrammingLanguage

PIM2 / /

Technology

matching algorithms / FPGA / 16 processors / 4 processors / matching algorithm / Flow control / iterative matching algorithms / SCLALABLE LEVEL-2 SWITCH Four processors / 4 MicroBlaze processors / caching / 80 processors / SRAM / Simulation / Quality of Service / local area networks / sequential iterative matching algorithm / iSLIP scheduling algorithm / CMP / /

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