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Superscalar
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#	Item
71	RISC vs. CISC – The Post-RISC Vasco Nuno Caio dos Santos Departamento de Informática, Universidade do Minho 4710 – 057 Braga, Portugal [removed] Add to Reading List Source URL: gec.di.uminho.pt Language: English - Date: 2002-01-26 10:53:05 Instruction set architectures Classes of computers Central processing unit Parallel computing Reduced instruction set computing Complex instruction set computing X86 Superscalar Instruction set Computer architecture Computing Computer engineering
72	Microsoft PowerPoint - HC18.630.S6T3.Design of a Reusable 1Ghz Superscalar ARM Processor.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:53:37 ARM architecture Classes of computers Parallel computing Instruction set architectures ARM Cortex-A8 Microarchitecture ARM11 Superscalar SIMD Computer architecture Electronic engineering Computing
73	AMX™ Timing Guide and Data for AMX MA32 Multitasking Executive First Printing: June 1, 2001 Add to Reading List Source URL: www.kadak.com Language: English - Date: 2002-11-01 16:01:00 Computing Computer memory AMC AMX Coupes CPU cache Instruction set Superscalar Microarchitecture Computer hardware Computer architecture Central processing unit
74	AMX™ Timing Guide and Data for AMXMultitasking Executive First Printing: January 11, 1994 Add to Reading List Source URL: www.kadak.com Language: English - Date: 2002-11-01 18:08:00 Computing Computer memory AMC AMX Coupes CPU cache Instruction set Superscalar Microarchitecture Cache Computer hardware Computer architecture Central processing unit
75	AMX™ Timing Guide and Data for AMX for ARM Multitasking Executive First Printing: Add to Reading List Source URL: www.kadak.com Language: English - Date: 2003-04-01 16:10:00 Central processing unit Classes of computers Computer memory Instruction set architectures AMC AMX CPU cache Instruction set ARM architecture Superscalar Computer architecture Computer hardware Computing
76	TX System RISC TX79 Core Architecture (Symmetric 2-way superscalar 64-bit CPU) Rev. 2.0 The information contained herein is subject to change without notice. Add to Reading List Source URL: www.lukasz.dk Language: English - Date: 2011-04-11 16:54:05 Computing Control register MIPS architecture Processor register Program counter CPU cache Reduced instruction set computing Instruction set Classic RISC pipeline Computer architecture Central processing unit Computer hardware
77	Static Classification for Dynamic Decisions Using Assembler Instrumentation Sylvain Aguirre University of Applied Science EIVD Add to Reading List Source URL: infoscience.epfl.ch Language: English - Date: 2011-07-09 03:33:46 Central processing unit Classes of computers Instruction set architectures Programming language implementation MIPS architecture Branch predictor Instruction set Assembly language Superscalar Computer architecture Computing Computer hardware
78	High-Performance Extendable Instruction Set Computing Heui Lee Asia Design Corporation [removed] Paul Beckett Add to Reading List Source URL: researchbank.rmit.edu.au Language: English Instruction set architectures Central processing unit Classes of computers Assembly languages Instruction set Reduced instruction set computing Superscalar Addressing mode Extendable instruction set computer Computer architecture Computing Computer engineering
79	18-447: Computer Architecture Lecture 12: Control Flow and Exceptions Prof. Onur Mutlu Carnegie Mellon University Spring 2012, [removed] Add to Reading List Source URL: www.ece.cmu.edu Language: English - Date: 2012-02-27 16:19:30 Central processing unit Branch predictor Microarchitecture Superscalar Computer architecture Computer engineering Computer hardware
80	10th Intl. Symp. on Asynchronous Circuits and Systems (ASYNC), Herakleion, Crete, Apr[removed]Hiding Synchronization Delays in a GALS Processor Microarchitecture∗ Greg Semeraro? , David H. Albonesi‡ , Grigorios Magklis Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-01 00:06:22 Central processing unit Alpha 21264 CPU cache Cycles per instruction Superscalar Microarchitecture Parallel computing FIFO Instruction set Computer architecture Computer hardware Computing

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