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Nios II / Nios embedded processor / Field-programmable gate array / Altera / CPU design / Joint Test Action Group / Reduced instruction set computing / Soft microprocessor / LatticeMico32 / Electronic engineering / Electronics / Computer hardware


HC17.S7T1 The Nios II Family of Configurable Soft-core Processors.ppt
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Document Date: 2013-07-27 23:47:48

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File Size: 1,31 MB

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Company

Nios II Embedded Systems / Altera Corporation / Tightly-Coupled Instruction Mem Pipeline Debug / /

Currency

cent / /

Facility

pipeline Nios II/f / Second port / One port / /

Organization

ASIC / /

Person

Purpose Registers I-Cache / James Ball August / Avalon Interconnect Off-chip / Configurable Soft-core Processors / Purpose Registers / /

Position

Interrupt Controller Control Registers Data Master D-cache Custom Instructions Tightly-Coupled Instruction Mem Arithmetic Logic Unit Tightly-Coupled Data Mem Tightly-Coupled Data Mem / Instruction Master Exception Controller / Controller General / /

Technology

FPGA / ASIC / SDRAM / operating systems / JTAG / /

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