Residue number system

Results: 26



#Item
1SPECIAL SECTION ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS  Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures R. Chaves and L. Sousa

SPECIAL SECTION ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures R. Chaves and L. Sousa

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Source URL: www.inesc-id.pt

Language: English - Date: 2007-09-28 04:23:33
    2RNS Reverse Converters based on the New Chinese Remainder Theorem I Hector Pettenghi Leonel Sousa

    RNS Reverse Converters based on the New Chinese Remainder Theorem I Hector Pettenghi Leonel Sousa

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2015-01-19 09:57:41
    3IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 10, OCTOBERwhere n is the stage gain, f is the clock frequency, VDD is the supply voltage, CCLK is the clock capacitance, N is the num

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 10, OCTOBERwhere n is the stage gain, f is the clock frequency, VDD is the supply voltage, CCLK is the clock capacitance, N is the num

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2013-09-24 07:27:55
    4A Compact and Scalable RNS Architecture Pedro Miguens Matutino Ricardo Chaves and Leonel Sousa  ISEL / INESC-ID / IST, Technical University of Lisbon

    A Compact and Scalable RNS Architecture Pedro Miguens Matutino Ricardo Chaves and Leonel Sousa ISEL / INESC-ID / IST, Technical University of Lisbon

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2014-01-29 04:45:59
    51  A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to prevent Power Analysis Side Channel Attacks Jude Angelo Ambrose†

    1 A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to prevent Power Analysis Side Channel Attacks Jude Angelo Ambrose†

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2013-12-23 08:24:26
    6DARNS:A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to prevent Power Analysis Side Channel Attacks Jude Angelo Ambrose  Hector Pettenghi, Leonel Sousa

    DARNS:A Randomized Multi-modulo RNS Architecture for Double-and-Add in ECC to prevent Power Analysis Side Channel Attacks Jude Angelo Ambrose Hector Pettenghi, Leonel Sousa

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2013-03-08 09:35:27
    7Method for designing modulo {2n ± k} Binary-to-RNS converters Hector Pettenghi1 , Ricardo Chaves1,2 and Leonel Sousa1,3 1  2

    Method for designing modulo {2n ± k} Binary-to-RNS converters Hector Pettenghi1 , Ricardo Chaves1,2 and Leonel Sousa1,3 1 2

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2013-12-23 08:09:57
    8J Sign Process Syst:191–205 DOIs11265An Efficient Scalable RNS Architecture for Large Dynamic Ranges Pedro Miguens Matutino · Ricardo Chaves ·

    J Sign Process Syst:191–205 DOIs11265An Efficient Scalable RNS Architecture for Large Dynamic Ranges Pedro Miguens Matutino · Ricardo Chaves ·

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2015-10-30 06:41:15
    9IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 6, JUNERNS Reverse Converters for Moduli Sets With Dynamic Ranges up to

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 6, JUNERNS Reverse Converters for Moduli Sets With Dynamic Ranges up to

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    Source URL: www.inesc-id.pt

    Language: English - Date: 2013-08-06 10:13:01