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RISC-V
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#	Item
11	Structure of the RISC-‐V So0ware Stack Sagar Karandikar UC Berkeley ! Add to Reading List Source URL: riscv.org - Date: 2016-04-09 11:41:57
12	Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Add to Reading List Source URL: www.iaik.tugraz.at - Date: 2016-02-24 05:00:01
13	RISC-V, Spike, and the Rocket Core CS250 Laboratory 2 (VersionWritten by Ben Keller Overview This lab will serve as an overview of several important technologies that have been developed by Add to Reading List Source URL: www-inst.eecs.berkeley.edu - Date: 2013-09-18 02:03:55
14	RISC-V “Rocket Chip” SoC Generator in Chisel Yunsup Lee UC Berkeley Add to Reading List Source URL: riscv.org - Date: 2016-04-09 11:41:57
15	PORTING NEW CODE TO RISC-V WITH YOCTO/OPENEMBEDDED Martin Maas () 1st RISC-V Workshop, January 15, 2015 Monterey, CA Add to Reading List Source URL: riscv.org Language: English - Date: 2016-04-09 11:41:57 Software System software Embedded Linux Build automation BitBake OpenEmbedded Yocto Project QEMU RISC-V Linux Cross compiler Wget
16	Ratio Games Raj Jain Washington University in Saint Louis Saint Louis, MOThese slides are available on-line at: Add to Reading List Source URL: www.cs.wustl.edu Language: English - Date: 2008-11-05 11:12:44 Computer architecture Religion Instruction set architectures Computing Classes of computers Reduced instruction set computing Raj Jain RISC-V Jain St. Louis
17	GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator Jan Gray Gray Research LLC, Bellevue, WA, USA Abstract— GRVI is an FPGA-efficient RISC-V RV32I soft Add to Reading List Source URL: fpga.org Language: English - Date: 2016-05-03 18:21:31 Computing Parallel computing Fabless semiconductor companies Reconfigurable computing Xilinx Field-programmable gate array Soft microprocessor Multi-core processor Altera
18	Efficient Cryptography on RISC-V Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-11-30 11:00:03 Computer architecture Instruction set architectures Computing Reduced instruction set computing RISC-V Cryptography Cryptographic primitive Instruction set Institute for Applied Information Processing and Communications
19	RISC-‐V Assembly Test Infrastructure Stephen Twigg UC Berkeley ! Add to Reading List Source URL: riscv.org Language: English - Date: 2016-04-09 11:41:57 BIOS Booting Interrupt
20	RISC-V Software Ecosystem Andrew Waterman UC Berkeley ! Tethered vs. Standalone Systems Add to Reading List Source URL: riscv.org Language: English - Date: 2016-04-09 11:41:57 Software Computer architecture System software Instruction set architectures RISC-V QEMU Reduced instruction set computing Kernel-based Virtual Machine Linux

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