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Microcode
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#	Item
61	TEACHING CONSOLE GAMES PROGRAMMING WITH THE SONY PLAYSTATION2 LINUX KIT Henry S Fortuna Add to Reading List Source URL: www.hsfortuna.pwp.blueyonder.co.uk Language: English - Date: 2010-02-04 05:38:23 PlayStation 2 PlayStation Central processing unit Video game development Linux for PlayStation 2 Emotion Engine Linux Microcode Game programming Sony Computer Entertainment Computing Computer architecture
62	GF20[removed]Data Processing Techniques Add to Reading List Source URL: bitsavers.trailing-edge.com Language: English - Date: 2013-01-19 21:34:15 Computer hardware Firmware Computing platforms Microcode Instruction set architectures Digital electronics IBM System/360 IBM System/3 Machine code Computer architecture Computing Central processing unit
63	Case Study: IBM5 SYSTEM[removed]ARCHITECTURE Add to Reading List Source URL: www.cs.tufts.edu Language: English - Date: 2008-05-19 19:28:54 Instruction set architectures IBM System/360 IBM System/370 IBM System/3 IBM System i IBM Word Operating system Microcode Computing Computer architecture Computing platforms
64	Volume 3, Spring Issue, 1990 N E C v. INTEL : B R E A K I N G N E W G R O U N D Add to Reading List Source URL: jolt.law.harvard.edu Language: English - Date: 2011-02-11 21:39:06 Central processing unit Firmware Microcode NEC V20 Intel X86 Computer architecture Computer hardware Computing
65	CRISP: A Pipelined 32b Microprocessor with 13Kb of Cache Memory Alan D. Berenbaumߤ, Brian W. Colbryߤߤ, David R. Ditzelߤߤ, R. Don Freemanߤߤ, Hubert R. McLellanߤߤ, Kevin J. O’Connorߤߤߤ, Masakazu Shojiߤߤ Add to Reading List Source URL: cm.bell-labs.com Language: English - Date: 2011-04-28 15:16:14 Computing R2000 Reduced instruction set computing Instruction set CPU cache Microcode Microprocessor Alpha 21264 Alpha 21064 Computer hardware Computer architecture Central processing unit
66	A Characterization of Processor Add to Reading List Source URL: emer.org Language: English - Date: 2007-07-22 18:34:31 Central processing unit Microcode Instruction set Microarchitecture CPU cache Addressing mode Cycles per instruction VAX Opcode Computer architecture Computer hardware Computer engineering
67	The Case for the Reduced Instruction Set Computer David A. Patterson Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2005-01-19 13:47:50 Central processing unit Instruction set architectures Classes of computers Reduced instruction set computing VAX Complex instruction set computing Instruction set Microcode IBM System/38 Computer architecture Computer engineering Computing
68	C S D Add to Reading List Source URL: www.cs.virginia.edu Language: English - Date: 2006-10-04 13:41:59 Central processing unit Firmware Microcode Control store Decoder Computer Control unit Whirlwind Instruction set Computer architecture Computer hardware Computing
69	The Case for the Reduced Instruction Set Computer David A. Patterson Add to Reading List Source URL: people.cs.umass.edu Language: English - Date: 2011-09-02 12:23:00 Central processing unit Instruction set architectures Classes of computers Reduced instruction set computing VAX Complex instruction set computing Instruction set Microcode IBM System/38 Computer architecture Computer engineering Computing
70	MicroVAX CPU CHIP DESIGN SPECIFICATION DC[removed]) Add to Reading List Source URL: robotron-vax.de Language: English - Date: 2010-05-26 17:25:49 Central processing unit Firmware Minicomputers MicroVAX Microcode VAX Microprocessors Control store Microsequencer Computer architecture Computer hardware Computing

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