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Central processing unit / Embedded microprocessors / OpenRISC / Instruction set architectures / CPU cache / ARM architecture / Microarchitecture / Instruction set / Computer hardware / Computer architecture / Electronic engineering


Document Date: 2012-05-26 19:35:20

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City

Reading / /

Company

Tensilica RISC / ARM10 / ARC / /

Facility

Integer Execution Pipeline / Store Unit / Store Access / Store Data / Store EA / /

IndustryTerm

medium and high performance networking / portable and networking applications / /

Organization

Load/Store Unit / MAC Unit / Instruction Unit / System Unit / Harvard / Floating Point Unit / /

Person

Julius Baxter / Damjan Lampret / Baxter OpenRISC / Arch Manual Damjan Lampret / /

Position

Major / Interrupt controller / Controller / /

RadioStation

Core / /

Technology

Caching / Floating Point Unit / virtual memory / operating system / DSP / RISC processors / /

SocialTag