Security Analysis of x86 Processor Microcode Daming D. Chen Gail-Joon Ahn Arizona State University

Source URL: www.dcddcc.com

• Central processing unit
• Microcode
• Advanced Micro Devices
• X86-64
• Instruction set
• Superscalar processor
• Microprocessor
• Microarchitecture
• X86
• Micro-operation
• Firmware
• Intel Core

Reducing Capacity and Conflict Misses using Set Saturation Levels Dyer Rol´an, Basilio B. Fraguela and Ram´on Doallo Grupo de Arquitectura de Computadores Departamento de Electr´onica e Sistemas Universidade da Coru˜

Source URL: www.des.udc.es

• Cache
• Central processing unit
• Computer architecture
• Computer memory
• CPU cache
• Virtual memory
• Cache algorithms
• Thrashing
• DSBC
• Memory hierarchy
• Microarchitecture
• Draft:Cache memory

Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering,

Source URL: www.dcs.warwick.ac.uk

• Cache
• Central processing unit
• Computer memory
• Computer architecture
• Parallel computing
• CPU cache
• Locality of reference
• Benchmark
• Microarchitecture
• Instruction set
• Instruction-level parallelism
• Draft:Cache memory

HexPADS: a platform to detect “stealth” attacks Mathias Payer Purdue University Abstract. Current systems are under constant attack from many different sources. Both local and remote attackers try to escalate their p

Source URL: hexhive.github.io

• Computer memory
• Computer architecture
• Central processing unit
• Cache
• CPU cache
• Parallel computing
• Row hammer
• Dynamic random-access memory
• Shared memory
• Microarchitecture
• Draft:Cache memory
• Cold boot attack

Appears in the proceedings of the 34th International Symposium on Microarchitecture (MICRO), Dec. 3-Dec. 5, 2001, Austin, Texas. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Ravi Rajwar a

Source URL: pages.cs.wisc.edu

• Concurrency control
• Computing
• Computer architecture
• Test-and-set
• Transactional memory
• Non-blocking algorithm
• Synchronization
• Monitor
• Lock
• Linearizability
• Consistency model
• CPU cache

Appears in the Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012 Neural Acceleration for General-Purpose Approximate Programs Hadi Esmaeilzadeh Adrian Sampson

Source URL: adriansampson.net

Appears in the Proceedings of the 34th International Symposium on Microarchitecture (MICRO), Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping Michael D. Powell, Amit Agarwal, T

Source URL: infoscience.epfl.ch

Profiling and Optimizing Micro-Architecture Bottlenecks on the Hardware Level Francis B. Moreira, Marco A. Z. Alves, Matthias Diener, Philippe O. A. Navaux Israel Koren

Source URL: euler.ecs.umass.edu

• Computer architecture
• Computing
• Computer engineering
• Central processing unit
• Instruction set architectures
• Cache
• Computer science
• Trace Cache
• Branch predictor
• Microarchitecture
• Prefetching
• ARM architecture

Appears in Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43), DecemberSampling Dead Block Prediction for Last-Level Caches Samira Khan∗ , Yingying Tian∗ , Daniel A

Source URL: taco.cse.tamu.edu

Microarchitecture-Directed Global Power Management for Multicore Processors Gene Y. Wu, Yi Yuan, Dan Zhang Department of Electrical and Computer Engineering The University of Texas at Austin {gwu,yyuan,dan.zhang}@mail.ut

Source URL: www.danzhang.net