<--- Back to Details
First PageDocument Content
Instruction set architectures / Power Architecture / CPU cache / Cache / Central processing unit / Computer memory / PowerPC / IBM POWER / Memory management unit / Computer architecture / Computer hardware / Computer engineering
Date: 2013-07-27 22:45:49
Instruction set architectures
Power Architecture
CPU cache
Cache
Central processing unit
Computer memory
PowerPC
IBM POWER
Memory management unit
Computer architecture
Computer hardware
Computer engineering

® MOTOROLA INC. PowerPCTM 601 Microprocessor

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 298,15 KB

Share Document on Facebook

Similar Documents

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE/ACM TRANSACTIONS ON NETWORKING 1 Milking the Cache Cow With Fairness

DocID: 1xVD7 - View Document

Computer security / Cryptography / Trusted computing / Computer architecture / X86 instructions / Elliptic curve cryptography / Enhanced privacy ID / Software Guard Extensions / Digital signature / Public-key cryptography / Trusted Execution Technology / CPU cache

CacheQuote: Efficiently Recovering Long-term Secrets of SGX EPID via Cache Attacks

DocID: 1xVnr - View Document

Cache / Computer architecture / Latency

RobinHood: Tail Latency-Aware Caching Dynamically Reallocating from Cache-Rich to Cache-Poor Daniel S. Berger (CMU) Joint work with: Benjamin Berg (CMU), Timothy Zhu (PennState), Siddhartha Sen (Microsoft Research), Mor

DocID: 1xV9M - View Document

Computing / Computer architecture / Computer engineering / Cache coherence / Cache coherency / Concurrent computing / Parallel computing / Cache / Controller / CPU cache

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

DocID: 1xUst - View Document

Computing / Computer architecture / Concurrent computing / Formal methods / Theoretical computer science / Cache coherency / Instruction set architectures / Concurrency / TLA+ / Model checking / Cache coherence / Specification language

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

DocID: 1xUq9 - View Document