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Central processing unit / Classes of computers / Instruction set architectures / Reduced instruction set computing / Berkeley RISC / Classic RISC pipeline / Instruction set / Addressing mode / MIPS architecture / Computer architecture / Computing / Computer engineering


REDUCED INSTRUCTION SET COMPUTERS Prof. Vojin G. Oklobdzija
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Document Date: 1999-10-16 23:46:51

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File Size: 81,26 KB

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Company

Sun Microsystems / International Business Machines / Silicon Graphics / IBM Corporation / Reduced Instruction Set Computer / Amdahl / /

Facility

Pipeline Flow / University of California Berkeley / RISC pipeline V.G. Oklobdzija Reduced Instruction Set Computers / RISC pipeline / Store Architecture Often / Stanford University / IBM T.J.Watson Research Center / Load/Store Pipeline / Store Architecture / Store Operation / /

IndustryTerm

technology advances / compiler technology / technology improvements / control hardware / logic technology / /

Organization

University of California / Instruction Decode Unit / Harvard / Stanford University / IBM T.J.Watson Research Center / Instruction Fetch Unit / /

Person

Vojin G. Oklobdzija / /

Position

PC/RT / E-Address Calculation WB / PC-RT / machine language programmer / spokesman / simple and straight forward / Memory Access WB / representative / General / /

ProvinceOrState

California / /

SportsLeague

Stanford University / /

Technology

Cache memory / logic technology / ROMP processor / compiler technology / /

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