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X86 / Interrupt descriptor table / Task state segment / Global Descriptor Table / Protected mode / CPUID / Processor register / Context switch / INT / Computer architecture / X86 architecture / Control register
Date: 2013-11-01 16:14:30
X86
Interrupt descriptor table
Task state segment
Global Descriptor Table
Protected mode
CPUID
Processor register
Context switch
INT
Computer architecture
X86 architecture
Control register

AMD64 Architecture Programmer’s Manual, Volume 2: System Programming

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