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Date: 2013-10-24 18:25:06Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86 | AMD64 Architecture Programmer’s Manual, Volume 2: System ProgrammingAdd to Reading ListSource URL: developer.amd.comDownload Document from Source WebsiteFile Size: 4,54 MBShare Document on Facebook |