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Shading / Image processing / Graphics hardware / Virtual reality / Shader / Rasterisation / Rendering / Deferred shading / Graphics pipeline / Computer graphics / 3D computer graphics / Imaging


PixelFlow: High-Speed Rendering Using Image Composition Steven Molnar, John Eyles, John Poulton Department of Computer Science University of North Carolina Chapel Hill, NC[removed]
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Document Date: 1998-06-11 15:58:40


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File Size: 192,10 KB

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City

Austin / Addison-Wesley / Reading / Mountain View / A VLSI / Daytona Beach / Pont-àMousson / /

Company

General Electric / Hewlett-Packard / Silicon Graphics / EMC / GE CIG Systems / Multiple Processor Z-Buffer Systems / Charles Stark Draper Labs / General Electric Company / VLSI Systems / Sun Microsystems / Intel / /

Country

France / Israel / /

Facility

Scripps Institute / Duke University / Computer Science University of North Carolina Chapel Hill / California Institute of Technology / BUNK89 Bunker / University of California / Local Port / Chapel Hill / /

IndustryTerm

image-composition network / 128x128 pixel processors / hardware token chain / conventional hardware / visibility algorithm / i860XP geometry processor / basic control algorithm / real time / pixel processor / image-composition systems / geometry processing / demanding applications / image composition network / memory chips / graphics systems / real-time systems / pipeline image-composition network / geometry processors / realtime systems / given rendering algorithm / floatingpoint processor / z-based image-composition network / identical custom chips / rasterization processors / compositor hardware / software components / control processor / real-time 3D graphics algorithms / imagecomposition network / software complexity / deferred shading with separate hardware / immediatemode graphics server / geometry processor / pixel processors / rasterization processor / Processor-per-primitive graphics systems / communication network / geometry processing/rasterization time / wiring for the image-composition network / /

Organization

Defense Advanced Research Projects Agency / John Poulton Department / Computer Science University / DARPA ISTO Order / Duke University / ASIC / University of California at Santa Cruz / California Institute of Technology / National Science Foundation / University of North Carolina / Scripps Institute / National Aeronautics and Space Administration / /

Person

E.P. Berlin / Jr. / Henry Fuchs / Kamran Eshrahian / John Eyles / Lee Westover / Neil Weste / Brice Tebbs / Jon Leech / Steven Molnar / B.M. Gelman / Anselmo Lastra / John Poulton / Turk / /

Position

compositor / Buffer VRAM Graphics Processor VRAM Graphics Processor VRAM Graphics Processor IGC Frame Buffer/ Compositor IGC Rasterizer/ Compositor Shader/ Compositor IGC Compositor Port Compositor / general / the compositor / Local Data Port Pixel Compositor Forward / Image Generation Controller / programmer / custom controller / Self-Terminating Low-Voltage Swing CMOS Output Driver / rasterizer and high-bandwidth compositor / pixel compositor / linear expression evaluator / Compositor Buffer Linear Expression Evaluator / /

ProgrammingLanguage

FL / /

ProvinceOrState

New York / California / Florida / North Carolina / Massachusetts / /

PublishedMedium

Computer Graphics / /

Technology

specific algorithm / chip design / Raster Graphics / A-buffer algorithms / cmp / programmable SIMD processors / 3D Graphics / SIMD shading processor / geometry processors / Deferred shading algorithms / virtual reality / shading algorithm / i860XP geometry processor / geometry processor / basic control algorithm / The geometry processor / floating-point processors / pixel processor / compositing algorithm / pixel processors / memory chips / real-time 3D graphics algorithms / 128x128 pixel processors / ASIC / load balancing / visibility algorithm / rasterization processor / given rendering algorithm / control processor / board design / 8-bit processors / simulation / rasterization processors / Parallel Processing / /

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