Back to Results
First PageMeta Content
Branch predictor / Branch misprediction / Assembly languages / Instruction set / Branch predication / Compiler optimization / ARM architecture / Processor register / Classic RISC pipeline / Computer architecture / Central processing unit / Instruction set architectures


Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications William Kreahling Western Carolina University
Add to Reading List

Document Date: 2006-04-21 21:30:19

Open Document

File Size: 127,10 KB

Share Result on Facebook

City

San Mateo / San Francisco / Atlanta / Jolla / Ottawa / AUSTIN / New York / /

Company

Prentice-Hall / Computer Systems / Digital Equipment Corporation / Hewlett Packard Laboratories / C Q Publishing Co. Ltd. / ACM Press / Morgan Kaufmann Publishers Inc. / /

Country

United States / Canada / United Kingdom / /

Currency

USD / /

/

Facility

SimpleScalar ARM port / Campus Drive / Future Work The pipeline / ARM port / Pipeline Diagram / Copyright Stephen Hines David Whalley Gary Tyson Florida State University / MEM stall / /

IndustryTerm

computing / energy / /

OperatingSystem

GNU / L3 / /

Organization

National Science Foundation / Florida State University / ID IF / Western Carolina University / /

Person

Stephen Hines David Whalley Gary / /

Position

representative / General / WB / /

ProgrammingLanguage

E / L / /

ProvinceOrState

California / /

Technology

encryption / adpcm / image compression / text-to-speech / ARM processor / System-on-Chip / MP3 / Terms Algorithms / Cmp / /

SocialTag