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Hardware description language / Cyclic redundancy check / Verilog / Logic synthesis / High-level synthesis / CRC / Register-transfer level / Checksum / Cksum / Electronic engineering / Electronic design automation / Digital electronics


Enhanced Reliability Design Automation Methodology considering the Generation of Parallel CRC Modules based on arbitrary CRC Polynomials and unlimited Data-Word Widths Timo Brenningmeyer University of Applied Sciences Os
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Document Date: 2012-04-13 13:29:50

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File Size: 502,62 KB

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Company

RTL / Applied Sciences Osnabrueck Laboratory / Ralf Göttsche Intel GmbH / /

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Facility

Data-Word Widths Timo Brenningmeyer University of Applied Sciences Osnabrueck Laboratory / Prof. Dr. Arno Ruckelshausen University of Applied Sciences Osnabrueck Laboratory / /

Organization

Arno Ruckelshausen University / Data-Word Widths Timo Brenningmeyer University of Applied Sciences Osnabrueck Laboratory of Micro / /

Person

Stefan Kuhnert / Norbert Förster / /

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Position

author / /

ProgrammingLanguage

Perl / Hardware Description Language / Verilog / /

PublishedMedium

IEEE Design & Test of Computers / IEEE Transactions on Computers / IEEE Transactions on Communications / /

Technology

Optoelectronics / Perl / Verilog / Parallel CRC generation methodology The algorithm / design flow The algorithm / /

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