<--- Back to Details
First PageDocument Content
Computing / Computer architecture / Computer memory / Transaction processing / Concurrency / Cache coherency / MESI protocol / Memory ordering / Consistency model / Cache coherence / Linearizability / Memory barrier
Date: 2014-10-12 15:57:01
Computing
Computer architecture
Computer memory
Transaction processing
Concurrency
Cache coherency
MESI protocol
Memory ordering
Consistency model
Cache coherence
Linearizability
Memory barrier

Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

Add to Reading List

Source URL: spcl.inf.ethz.ch

Download Document from Source Website

File Size: 1,26 MB

Share Document on Facebook

Similar Documents

spcl.inf.ethz.ch @spcl_eth TIMO SCHNEIDER <>  DPHPC Recitation Session 3

spcl.inf.ethz.ch @spcl_eth TIMO SCHNEIDER <> DPHPC Recitation Session 3

DocID: 1rgnX - View Document

An Equal Opportunity / Affirmative Action Agency Permit Application Office of Parks, Recreation and Historic Preservation

An Equal Opportunity / Affirmative Action Agency Permit Application Office of Parks, Recreation and Historic Preservation

DocID: 1raJ0 - View Document

Design of Parallel and High Performance Computing HS 2014 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich

Design of Parallel and High Performance Computing HS 2014 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich

DocID: 1r67n - View Document

spcl.inf.ethz.ch @spcl_eth TIMO SCHNEIDER <>  DPHPC Recitation Session 3

spcl.inf.ethz.ch @spcl_eth TIMO SCHNEIDER <> DPHPC Recitation Session 3

DocID: 1qVac - View Document

Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance

DocID: 1qSE1 - View Document