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CVA
Results: 440

#	Item
151	SYNERGISTIC CACHING IN SINGLE-CHIP MULTIPROCESSORS a dissertation submitted to the department of electrical engineering and the committee on graduate studies Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Cache Computer architecture Central processing unit Computer engineering Microprocessors CPU cache Microarchitecture Computer memory Computer hardware Computing
152	RESOURCE MANAGEMENT IN SINGLE-CHIP MULTIPROCESSORS a dissertation submitted to the department of computer science and the committee on graduate studies Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05
153	Design Tradeoffs for Tiled CMP On-Chip Networks ∗ James Balfour , William J. Dally Computer Systems Laboratory Stanford University Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2006-09-12 12:06:57 Computer networking Network performance Throughput Network switch Routing Packet switching Channel Router Asynchronous Transfer Mode Computing Electronic engineering Network architecture
154	Scalable Opto-Electronic Network (SOENet) Amit K. Gupta, William J. Dally, Arjun Singh, and Brian Towles Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Electronics Switched fabric Fat tree InfiniBand Routing Topology Ethernet Clos network Node Network topology Computing Network architecture
155	WMF2EPS 1.31 : WMF->EPS conversion for indep_contrib.emf Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Throughput Routing algorithms Computing Wireless networking Telecommunications engineering Network performance Routing Routing protocols
156	Microsoft Word - vlsi2004_main.doc Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Oscillators Electronic design Radio electronics Integrated circuits Digital electronics Voltage-controlled oscillator Phase-locked loop Jitter Analog-to-digital converter Electronic engineering Electronics Electromagnetism
157	Delay and Buffer Bounds in High Radix Interconnection Networks Abstract queues is a known hard problem. The difficulty in analysis primarily arises from the fact that the traffic processes do Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Electronic engineering Queuing delay Quality of service Traffic flow Queueing theory Throughput Leaky bucket TCP global synchronization Network performance Statistics Management
158	A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Routing Flow control Network On Chip Wormhole switching Throughput Network switch Router Traffic flow Channel Network architecture Computing Electronic engineering
159	IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 11, NOVEMBERLow-Power Area-Efficient High-Speed I/O Circuit Techniques Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Electronic design Integrated circuits Digital electronics Oscillators Electronic circuits Inverter Analog-to-digital converter Phase-locked loop CMOS Electronic engineering Electronics Electromagnetism
160	Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:20:06 Network performance OSI protocols Inter-process communication Traffic flow Throughput Network architecture Transmission Control Protocol Wormhole switching Packet switching Computing Computer networking Streaming

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