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Wormhole switching
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1	PS-1 Ultra Low-Power High-Speed Flexible Probabilistic Adder for Error-Tolerant Applications Add to Reading List Source URL: www.bpti.lt Language: English - Date: 2013-12-16 08:28:50 Computing Network architecture Computer networking Internet Routing Wormhole switching Transmission Control Protocol Router Packet switching Packet loss Routing table
2	194 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 3, NO. 2, MARCH 1992 Virtual-Channel Flow Control William J. Dally, Member, IEEE Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:16:32 Network architecture Flow control Network protocols Network On Chip Routing Wormhole switching Throughput Packet switching Channel Computing Computer networking Data transmission
3	/afs/ir.stanford.edu/users/a/r/arjuns/work/research/TOR_NN/RESULTS/HILAT/VAL_13.eps Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Latency Wormhole switching Algorithm Computing Electronic engineering Engineering Network performance Routing Throughput
4	IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:17:54 Electronics Information theory Network performance Low latency Wormhole switching Network topology Routing Channel Packet switching Electronic engineering Telecommunications engineering Computing
5	A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Routing Flow control Network On Chip Wormhole switching Throughput Network switch Router Traffic flow Channel Network architecture Computing Electronic engineering
6	Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:20:06 Network performance OSI protocols Inter-process communication Traffic flow Throughput Network architecture Transmission Control Protocol Wormhole switching Packet switching Computing Computer networking Streaming
7	Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Computer networking Computer memory Ethernet Network switch Content-addressable memory Cell Wormhole switching Network On Chip Computing Electronic engineering Electronics
8	775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:18:56 Information Low latency Electronic engineering Throughput Wormhole switching Channel Latency Routing Network topology Information theory Network performance Computing
9	A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Network On Chip Routing Wormhole switching OSI protocols Throughput Router Network switch Forwarding plane Load-balanced switch Network architecture Computing Flow control
10	In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Wormhole switching Computing OSI protocols Electronic engineering Network performance Streaming Throughput Latency Scheduling Flow control Network On Chip Routing