Back to Results
First PageMeta Content
Computing / R2000 / Reduced instruction set computing / Instruction set / CPU cache / Microcode / Microprocessor / Alpha 21264 / Alpha 21064 / Computer hardware / Computer architecture / Central processing unit


CRISP: A Pipelined 32b Microprocessor with 13Kb of Cache Memory Alan D. Berenbaumߤ, Brian W. Colbryߤߤ, David R. Ditzelߤߤ, R. Don Freemanߤߤ, Hubert R. McLellanߤߤ, Kevin J. O’Connorߤߤߤ, Masakazu Shojiߤߤ
Add to Reading List

Document Date: 2011-04-28 15:16:14


Open Document

File Size: 58,07 KB

Share Result on Facebook

City

Holmdel / Allentown / Goncalves / Palo Alto / /

Company

Patterson / Parillo L. C. / AT&T Bell Laboratories / /

IndustryTerm

metal / off-chip / co-processors / physical chip / slave chips / software requirements / compiler technology / software changes / on-chip / caches on-chip / software control / continuous metal / /

Movie

A. D. / /

OperatingSystem

Unix / /

Organization

Execution Unit / Prefetch Decode Unit / /

Person

Brian W. Colbry / R. Don Freeman / Addison Wesley / David R. Ditzel / H. J. De / Murray Hill / Alan D. Berenbaum / Masakazu Shoji / Domino / T. Szymanski / Hubert R. McLellan / A. G. Fraser / V / /

Position

Goalie / eliminating programmer / physical geometry layout editor / tty driver / interpreter / programmer / /

ProgrammingLanguage

C / /

ProvinceOrState

California / N. F. / /

PublishedMedium

The Bell System Technical Journal / /

Technology

modified Booth algorithm / MIPS Computer Systems R2000 processor / Unix / same technology / resulting processor / RISC Processor / mature 1.75µ twin-tub4 CMOS technology / Cache Memory / Unix operating system / caching / 1.75µ CMOS technology / simulation / 30 chips / IO protocol / virtual memory / Operating Systems / physical chip / Integrated Circuits / 1-cycle IO protocol / caches on-chip / compiler technology / CAD / 16 MHz chip / been fabricated using a mature 1.75µ twin-tub4 CMOS technology / /

SocialTag