<--- Back to Details
First PageDocument Content
Computer engineering / ARM architecture / CPU cache / Compiler optimization / Instruction set / Branch predication / Microarchitecture / Jazelle / X86 assembly language / Computer architecture / Computer hardware / Central processing unit
Date: 2005-07-27 04:52:35
Computer engineering
ARM architecture
CPU cache
Compiler optimization
Instruction set
Branch predication
Microarchitecture
Jazelle
X86 assembly language
Computer architecture
Computer hardware
Central processing unit

Profile Guided Selection of ARM and Thumb Instructions Arvind Krishnaswamy

Add to Reading List

Source URL: www.cs.arizona.edu

Download Document from Source Website

File Size: 97,03 KB

Share Document on Facebook

Similar Documents

Call for Papers The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas

DocID: 1vnsx - View Document

Microarchitecture and Compiler Techniques for Dual Width ISA processors by Arvind Krishnaswamy

DocID: 1uu0D - View Document

Appears in the Proceedings of the 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015 Neural Acceleration for GPU Throughput Processors Amir Yazdanbakhsh Jongse Park Hardik Sharma

DocID: 1utmS - View Document

Microarchitecture of a High-Radix Router John Kim, William J. Dally, Brian Towles1, Amit K. Gupta 1 Computer Systems Laboratory D.E. Shaw Research and Development Stanford University, Stanford, CA 94305

DocID: 1us9B - View Document

Published in the Proceedings of the 32nd International Symposium on Microarchitecture, NovemberDIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design Todd M. Austin1 Advanced Computer Architecture

DocID: 1ucAH - View Document