| Document Date: 2009-01-11 13:30:20
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City Paceline / / Company Checkpoint / Sun Microsystems / CTV / RTL / Checker Persistence Functional Correctness Checking Granularity Delay Trading / Amdahl / Craig Zilles / / / Facility Computer Engineering University of Illinois / Pipeline Fix / Checkpoint Interval / pipeline PE / Checkpoint Restoration Overhead / / IndustryTerm optimization algorithm / less energy-efficient variant / parallel systems / energy / design optimization algorithm / individual applications / average switching energy / in-order processor / vpr applications / correction hardware / / Organization National Science Foundation / UIUC OpenSPARC Center of Excellence / University of Illinois / SESC / / Person Cadence Encounter / Jeffrey J. Cook / done using Cadence Encounter / / Position 10GB/s max Paceline Parameters Razor Parameters Max Leader / 16KB WB / General / head / 64B line Scheduler / designer / 2MB WB / representative / / Product Razor / BlueShift / Transplant tool / SPECint2000 applications / Transplant / SPECint2000 / / ProvinceOrState Prince Edward Island / / Technology TS Microarchitectures Conventional processors / PCT algorithm / 529 4 Designing Processors / TS processors / design optimization algorithm / optimization algorithm / CMP / in-order processor / gate-level BlueShifted processor / OpenSPARC T1 processor / simulation / CAD / /
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BlueShift: Designing Processors for Timing Speculation from the Ground Up∗ Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles Departments of Computer Science and o