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11	A Novel ASIC Design Approach Based on a New Machine Paradigm R. W. Hartenstein, A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber Universitaet Kaiserslautern, F.B. Informatik, Bau 12, Postfach 3049, DKaisers Add to Reading List Source URL: www.fpl.uni-kl.de - Date: 2016-01-22 06:43:29
12	A Novel ASIC Design Approach Based on a New Machine Paradigm R. W. Hartenstein, A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber Universitaet Kaiserslautern, F.B. Informatik, Bau 12, Postfach 3049, DKaisers Add to Reading List Source URL: www.fpl.uni-kl.de - Date: 2013-11-13 03:37:58
13	南京拓微集成电路有限公司 NanJing Top Power ASIC Corp. TP4056 1A Standalone Linear Li-lon Battery Charger with Thermal Regulation in SOP-8 DESCRIPTION Add to Reading List Source URL: dlnmh9ip6v2uc.cloudfront.net - Date: 2013-01-09 18:15:52
14	南京拓微集成电路有限公司 NanJing Top Power ASIC Corp. TP4056 1A Standalone Linear Li-lon Battery Charger with Thermal Regulation in SOP-8 DESCRIPTION Add to Reading List Source URL: www.electrodragon.com - Date: 2013-10-15 11:01:11
15	A Novel ASIC Design Approach Based on a New Machine Paradigm R. W. Hartenstein, A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber Universitaet Kaiserslautern, F.B. Informatik, Bau 12, Postfach 3049, DKaisers Add to Reading List Source URL: www.fpl.uni-kl.de - Date: 2012-10-24 05:06:52
16	SMBDirect Latency on Windows Server 2012 R2 Realize Full SSD Storage Performance with T5 RDMA over Ethernet Executive Summary Chelsio’s Terminator 5 ASIC RDMA over Ethernet (iWARP) implementation provides high performa Add to Reading List Source URL: www.chelsio.com - Date: 2014-11-11 14:05:47
17	eSi-3200 – 32-bit, low-cost & low-power CPU EnSilica’s eSi-3200 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs with on-chip memories. The eSi-3 Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:26 Computing Computer architecture Embedded microprocessors Electronics ESi-RISC EnSilica Instruction set architectures Soft microprocessor Nios II
18	eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:25 Computing Computer architecture Computer engineering Embedded microprocessors Instruction set architectures EnSilica ESi-RISC Central processing unit JTAG ARC 16-bit Reduced instruction set computing
19	Efficient ASIC Implementation of a Real-Time Depth Mapping Stereo Vision System Michael Kuhn1 (Student), Stephan Moser1 (Student), Oliver Isler1 (Student), Frank K. G¨urkaynak2 , Andreas Burg2 , Norbert Felber2 , Hubert Add to Reading List Source URL: disco.ethz.ch Language: English - Date: 2014-09-26 08:36:31 Image processing Computing Video Graphics Array Tegra Computer vision Computer architecture Computer hardware
20	Design of a Power Optimal Reversible FIR Filter ASIC Speech Signal Processing Yelle Harika M.Tech, Joginpally B.R.Engineering College. Add to Reading List Source URL: www.ijmetmr.com Language: English - Date: 2016-08-16 07:16:56 Computer arithmetic Theoretical computer science Arithmetic Digital circuits Electronic engineering Logic gates Adder Binary logic Models of computation Dadda multiplier Carry-select adder Carry-lookahead adder

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