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Computing / ARM Cortex-A15 MPCore / Multi-core processor / Tegra / CPU cache / A15 / Computer architecture / ARM architecture / Computer hardware


A Power-Centric Timing Optimization Flow for a Quad-Core ARM Cortex-A7 Processor Bernard Ortiz de Montellano Product Manager Processor Division
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Document Date: 2014-11-07 12:39:16


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File Size: 4,04 MB

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GPU / Synopsys / /

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energy-efficient v7A / energy-efficient applications processor / energy / /

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Dale Lomelino / /

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Staff Applications Consultant / Product Manager / Manager Processor Division / /

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A7 MPCore™ Processor / /

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Core / /

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Floating Point Unit / application processor / 4 processor / System-on-Chip / applications processor / de Montellano Product Manager Processor / smartphones / smartphone / Cortex-A15 processor / /

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