BUILDING A POWER OPTIMIZATION POOL / IL ECE Department University of Colorado Boulder / University of Wisconsin-Madison / /
IndustryTerm
globallyoptimal search / search process / trial-and-error search space evaluation / recent industry processors / optimization algorithm / near-optimal solutions / on-chip bus network / multi-core processors / application-specific superscalar processors / system-level software / large search space / knapsack algorithm / multi-core systems / extra hardware / run-time management / model directed search / on-line performance/power modeling / temperature management / method using greedy search / out-of-order processors / multi-core processor / multi-configuration hardware / large search-space / actual physical hardware / thermal management / energy / multicore processors / online phase detection approach / Greedy algorithms / energy-efficiency / evaluation algorithm / Memory-bound applications / software implementation / power management / greedy search / long search process / out-oforder processors / greedy algorithm / Compute-bound applications / individual processor / technology scaling / on-line models / processor-wide energy-savings / energy efficiency / selection algorithms / on-line microarchitecture adaptation / search space / on-chip / search time / simulation infrastructure / brute-force optimal search / /
MarketIndex
SPEC CPU2000 / /
OperatingSystem
L3 / /
Organization
National Science Foundation / IL ECE Department University of Colorado Boulder / Northwestern University / Semiconductor Industry Association / US Federal Reserve / University of Wisconsin / /
Person
Max Off-chip / D. Brooks / V / Max Perf-Loss / Robert P. Dick / Russ Joseph / / /
Position
power manager / trial-and-error power manager / manager to a small subset / manager / manager code / global power manager / Representative / /
Product
Xeon processor / /
ProgrammingLanguage
C / /
ProvinceOrState
Wisconsin / Ontario / /
PublishedMedium
Microprocessor Report / /
RadioStation
Core / /
Technology
Alpha / Virtual Machine / RAM / out-of-order processors / CMP system / 90-nm Itanium Family processor / D. art mcf parser vpr Processor / multicore processors / operating system / Operating Systems / optimization algorithm / CMP / recent industry processors / 5.1 Processor / On-line evaluation algorithm / application-specific superscalar processors / Experimentation Keywords Chip Multi-Processor / B. applu gap facerec vortex Processor / out-oforder processors / 64-bit Xeon processor / greedy algorithm / selection algorithms / simulation / knapsack algorithm / /
Multi-Optimization Power Management for Chip Multiprocessors Ke Meng, Russ Joseph, Robert P. Dick Li Shang