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Computing / Cache / Real-time computing / Worst-case execution time / CPU cache / Instruction set / Latency / NOP / Computer performance / Computer architecture / Central processing unit / Computer hardware


What is a Timing Anomaly? Franck Cassez1 , René Rydhof Hansen∗2 , and Mads Chr. Olesen2 1 National ICT Australia Sydney, Australia
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Document Date: 2012-10-25 20:20:08

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File Size: 547,19 KB

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City

Sydney / /

Company

Creative Commons / More Favorable Hardware / Dagstuhl Publishing / Embedded Systems / Billy / /

Country

Australia / Germany / /

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IndustryTerm

hardware systems / concrete reference hardware / out-of-order processor / concrete hardware / real-time systems / anomaly free hardware / /

MusicGroup

Yes / /

Organization

Danish Research Council for Technology and Production / Multi-Cycle Integer Unit / Aalborg University / Department of Computer Science / Integer Unit / /

Person

Franck Cassez / René Rydhof Hansen / Bill Editors / Mads Chr / Selma Lagerlöfs Vej / /

Position

Author / Editor / Prime Minister / Conditional exec. / /

ProgrammingLanguage

Java / /

TVStation

WCET / /

Technology

real processor / out-of-order processor / Java / Digital Object Identifier / /

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