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Computer hardware / Computer architecture / Central processing unit / Bayesian network / Networks / CPU cache / Worst-case execution time / Graphical model / Cache / Statistics / Bayesian statistics / Statistical models


Learning Bayesian Networks for Improved Instruction Cache Analysis Mark Bartlett, Iain Bate and James Cussens Department of Computer Science University of York Heslington, York, UK
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Document Date: 2011-01-04 06:19:45

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City

Tallahassee / San Francisco / /

Company

Bayesian Networks / Embedded Computing Systems / Real-Time Systems / /

Country

United Kingdom / /

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Facility

University of York / Computer Science University of York Heslington / Florida State University / /

IndustryTerm

software interdependencies / idealised correct network / potential solution / safety critical systems / final network / exhaustive search / search space / learning algorithm / /

Organization

University of York / Florida State University / Computer Science University of York Heslington / Service of Mankind / James Cussens Department / /

Person

Conflict Meaning / James Cussens / Mark Bartlett / Morgan Kaufmann / /

ProvinceOrState

Florida / California / /

PublishedMedium

the Worst Case Execution Times / /

TVStation

WCET / reasoning about the WCET / /

Technology

learning algorithm / ALPHA processor / artificial intelligence / caching / machine learning / simulation / real chips / /

URL

http /

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