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Wormhole
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#	Item
31	IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:17:54 Electronics Information theory Network performance Low latency Wormhole switching Network topology Routing Channel Packet switching Electronic engineering Telecommunications engineering Computing
32	A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Routing Flow control Network On Chip Wormhole switching Throughput Network switch Router Traffic flow Channel Network architecture Computing Electronic engineering
33	Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:20:06 Network performance OSI protocols Inter-process communication Traffic flow Throughput Network architecture Transmission Control Protocol Wormhole switching Packet switching Computing Computer networking Streaming
34	Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Computer networking Computer memory Ethernet Network switch Content-addressable memory Cell Wormhole switching Network On Chip Computing Electronic engineering Electronics
35	775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:18:56 Information Low latency Electronic engineering Throughput Wormhole switching Channel Latency Routing Network topology Information theory Network performance Computing
36	A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Network On Chip Routing Wormhole switching OSI protocols Throughput Router Network switch Forwarding plane Load-balanced switch Network architecture Computing Flow control
37	King Address March 2006 Richard P. Olenick In 1978 Andrei Voznesensky toured the United States providing Americans with a glimpse of Soviet life through his poetry readings. I was fortunate to be in one such audience whi Add to Reading List Source URL: phys.udallas.edu Language: English - Date: 2007-09-07 00:35:24 Time travel Relativity Space Time Nostalgia Spacetime Wormhole Closed timelike curve Physics Dimension Lorentzian manifolds
38	In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:05 Wormhole switching Computing OSI protocols Electronic engineering Network performance Streaming Throughput Latency Scheduling Flow control Network On Chip Routing
39	Stanford University Concurrent VLSI Architecture Memo 124 Elastic Buffer Networks-on-Chip George Michelogiannakis∗, James Balfour and William J. Dally Concurrent VLSI Architecture Group Computer Systems Laboratory Stan Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-08-26 22:57:32 Computing Router Network switch Hop count Throughput Network On Chip Transmission Control Protocol Wormhole switching Network architecture Routing Electronic engineering
40	In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan, 2001, Monterrey, Mexico, ppBest Student Paper Award) A Delay Model and Speculative Architecture for Pip Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Flow control Network On Chip Routing Wormhole switching Network performance Throughput Network switch Router Traffic flow Network architecture Computing Electronic engineering