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Physical design / Integrated circuit design / Floorplan / Placement / Standard cell / Application-specific integrated circuit / Timing closure / Signal integrity / Joint Test Action Group / Electronic engineering / Electronic design automation / Electronics


Design Planning Strategies to Improve Physical Design Flows— Floorplanning and Power Planning August 2003
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Document Date: 2014-11-07 14:32:47

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File Size: 199,33 KB

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Company

Hercules / RTL / Synopsys Inc. / TSMC / Chip Level Global Route Budgeting Export / Synopsys Professional Services / /

Event

Force Majeure / /

IndustryTerm

system-on-chip / metal wires / metal / design tools / technology nodes / metal straps / large chips / target process technology / process technology / charge-collecting metal / high metal layers / µm technology serves / silicon real estate / power distribution network / metal line / mainstream chips / technology node / metal rings / large metal areas / metal atoms / metal width / power-mesh metal / metal layers / larger chip / manufacturing handoffs / metal lines / metal grain boundaries / metal wire width decreases / /

Organization

ASIC / US Federal Reserve / Design Center / /

Person

Steve Lloyd / Jon Young / Ron Spillman / Rick Mitchell / Sachin Idgunji / /

Position

designer / Manager / Staff Engineer / /

Product

Astro-Xtalk / /

ProgrammingLanguage

Perl / /

Technology

5-Mgate chip / ASIC / flash memory / mainstream chips / 0.13µm technology / system-on-chip / JTAG / larger chip / target process technology / Perl / existing chip / process technology / /

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