A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM Yoongu Kim Vivek Seshadri Donghyuk Lee - Synchronous dynamic random-access memory - Document - PDFSEARCH.IO - Document Search Engine

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	A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM Yoongu Kim Vivek Seshadri Donghyuk Lee Add to Reading List Document Date: 2012-04-29 12:14:30 Open Document File Size: 927,28 KB Share Result on Facebook Company IBM / Fujitsu / Rambus / DATA Bank / R/W Bank / Rank Bank / Additional SA SEL / PRECHARGE Bank / Intel / ACTIVATE / / Country Sudan / / Currency AMD / / Event Product Issues / / Facility Intel Sandy Bridge / Sandy Bridge / / IndustryTerm overall bank count / 55nm technology / proposed memory scheduling algorithms / baseline scheduling algorithm / subarrays-per-bank / subarrays-per-bank increases / bank access latencies / multi-core systems / rightmost applications / manufacturing constraints / bank conflicts / accessible subarray / bank wastes power / multicore systems / energy / large bank / bank conflict problem / ith bank / energy consumption / main memory systems / banks-per-chip / energy-efficiency / energy cost / bank conflict / leftmost applications / process technology / bank share / subarrays-per-bank captures / bank / bank access latency / per-bank circuit components / bank address / frequent bank conflicts / application-aware memory scheduling algorithms / bank serialization / bank access / bank write-recovery2 / bank operation / higher energy savings / bank organization / bank-level parallelism / / NaturalFeature tCCD R(W) R(W) Channel / / Organization ACTIVATE Row / etc / Logical Organization / Subarray-Select Command / Baseline SALP / IN V / Based / Carnegie Mellon University / Physical Organization of Banks Although / 14tCK Organization / / Person Kim Vivek Seshadri Donghyuk Lee Jamie Liu / Lee Jamie Liu Onur Mutlu Carnegie / / Position VP / I/O driver / scheduler / memory controller / controller / FR-FCFS scheduler / controller / / Product rows / row / / ProgrammingLanguage Verilog / / ProvinceOrState Oregon / / RadioStation Core / / Technology DDR3 chip / chip design / baseline scheduling algorithm / 55nm technology / 55nm process technology / using 55nm technology / larger capacity DRAM chips / eight DRAM chips / SRAM / also proposed memory scheduling algorithms / process technology / application-aware memory scheduling algorithms / Verilog / two chips / 8 Processor / SDRAM / DRAM chips / DRAM chip / 2Gb DRAM chip / 8 banks-per-chip / / SocialTag Dynamic random-access memory Synchronous dynamic random-access memory CAS latency SDRAM latency Serial presence detect Memory controller DDR3 SDRAM Random-access memory CPU cache Computer memory